OP37GPZ Datasheet, PDF (5/16 Pages) Analog Devices – Low Noise, Precision, High Speed tional Amplifier

BINDING DIAGRAM
1. NULL
1
2. (–) INPUT
3. (+) INPUT
4. V–
1990
6. OUTPUT
1427U
7. V+
8 ^{8. NULL}
OP37
2
3
7
4
6
Wafer Test Limits (VS = ؎15 V, TA = 25؇C for OP37N, OP37G, and OP37GR devices; TA = 125؇C for OP37NT and OP37GT devices,
unless otherwise noted.)
Parameter
Symbol
Input Offset
Voltage
Input Offset
Current
Input Bias
Current
Input Voltage
Range
Common Mode
Rejection Ratio
V_OS
I_OS
I_B
IVR
CMRR
OP37NT
Conditions Limit
Note 1
60
50
± 60
± 10.3
V_CM = ± 11 V 108
OP37N
Limit
35
35
± 40
± 11
114
OP37GT
Limit
200
85
± 95
± 10.3
100
OP37G OP37GR
Limit Limit
60
100
50
75
± 55
± 80
± 11
± 11
106
100
Unit
mV MAX
nA MAX
nA MAX
V MIN
dB MIN
Power Supply
Rejection Ratio PSRR
Large-Signal
Voltage Gain A_VO
Output Voltage
Swing
V_O
Power
Consumption P_d
T_A = 25∞C,
V_S = ± 4 V to
± 18 V
10
T_A = 125∞C,
V_S = ± 4.5 V to
± 18 V
16
R_L ≥ 2 kW,
V_O = ± 10 V 600
R_L ≥ 1 kW,
V_O = ± 10 V
R_L ≥ 2 kW
R_L ≥ 600 kW
± 11.5
V_O = 0
10
10
20
1000
500
800
± 12
± 11
± 10
140
10
20
1000
800
± 12
± 10
140
700
± 11.5
± 10
170
mV/V MAX
mV/V MAX
V/mV MIN
V/mV MIN
V MIN
V MIN
mW MAX
NOTES
For 25∞C characterlstics of OP37NT and OP37GT devices, see OP37N and OP37G characteristics, respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
–5–