MT-086 Datasheet, PDF (5/10 Pages) Analog Devices – Fundamentals of Phase Locked Loops (PLLs)

MT-086
3. The value loaded to the B counter must always be greater than that loaded to the A
counter.
Assume that the B counter has just timed out and both counters have been reloaded with the
values A and B. Let’s find the number of VCO cycles necessary to get to the same state again.
As long as the A counter has not timed out, the prescaler is dividing down by P + 1. So, both the
A and B counters will count down by 1 every time the prescaler counts (P + 1) VCO cycles. This
means the A counter will time out after ((P + 1) × A) VCO cycles.
At this point the prescaler is switched to divide-by-P. It is also possible to say that at this time the
B counter still has (B – A) cycles to go before it times out. How long will it take to do this:
((B – A) × P).
The system is now back to the initial condition where we started.
The total number of VCO cycles needed for this to happen is :
N = [A × (P + 1)] + [(B – A) × P]
= AP + A + BP – AP
= BP + A.
Therefore, F_OUT = (F_REF/R) × (BP + A), as in Figure 4.
There are many specifications to consider when designing a PLL. The input RF frequency range
and the channel spacing determine the value of the R and N counter and the prescaler
parameters.
The loop bandwidth determines the frequency and phase lock time. Since the PLL is a negative
feedback system, phase margin and stability issues must be considered.
Spectral purity of the PLL output is specified by the phase noise and the level of the reference-
related spurs.
Many of these parameters are interactive; for instance, lower values of loop bandwidth lead to
reduced levels of phase noise and reference spurs, but at the expense of longer lock times and
less phase margin.
Because of the many tradeoffs involved, the use of a PLL design program such as the Analog
Devices' ADIsimPLL™ allows these tradeoffs to be evaluated and the various parameters
adjusted to fit the required specifications. The program not only assists in the theoretical design,
but also aids in parts selection and determines component values.
OSCILLATOR/PLL PHASE NOISE
A PLL is a type of oscillator, and in any oscillator design, frequency stability is of critical
importance. We are interested in both long-term and short-term stability. Long-term frequency
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