MT-086 Datasheet, PDF (1/10 Pages) Analog Devices – Fundamentals of Phase Locked Loops (PLLs)

MT-086
TUTORIAL
Fundamentals of Phase Locked Loops (PLLs)
FUNDAMENTAL PHASE LOCKED LOOP ARCHITECTURE
A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a
phase comparator so connected that the oscillator maintains a constant phase angle relative to a
reference signal. Phase-locked loops can be used, for example, to generate stable output high
frequency signals from a fixed low-frequency signal.
Figure 1A shows the basic model for a PLL. The PLL can be analyzed as a negative feedback
system using Laplace Transform theory with a forward gain term, G(s), and a feedback term,
H(s), as shown in Figure 1B. The usual equations for a negative feedback system apply.
ERROR DETECTOR
LOOP FILTER
VCO
PHASE
DETECTOR
CHARGE
PUMP
(A) PLL MODEL
FEEDBACK DIVIDER
F_O = N F_REF
(B) STANDARD NEGATIVE FEEDBACK
CONTROL SYSTEM MODEL
Figure 1: Basic Phase Locked Loop (PLL) Model
The basic blocks of the PLL are the Error Detector (composed of a phase frequency detector and
a charge pump), Loop Filter, VCO, and a Feedback Divider. Negative feedback forces the error
signal, e(s), to approach zero at which point the feedback divider output and the reference
frequency are in phase and frequency lock, and F_O = N_FREF.
Referring to Figure 1, a system for using a PLL to generate higher frequencies than the input, the
VCO oscillates at an angular frequency of ω_O. A portion of this signal is fed back to the error
detector, via a frequency divider with a ratio 1/N. This divided down frequency is fed to one
input of the error detector. The other input in this example is a fixed reference signal. The error
detector compares the signals at both inputs. When the two signal inputs are equal in phase and
frequency, the error will be constant and the loop is said to be in a “locked” condition.
Rev.0, 10/08, WK
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