CN-0232 Datasheet, PDF (5/6 Pages) Analog Devices – Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and an External PLL Circuit

Circuit Note
Initialization Procedure
The ADF4350 must go through the band select process for every
new frequency.
1. Initialize the ADF4350 as normal (program R5, R4, R3, R2,
R1, R0), except set DB4, R2 to 1 (ICP three-state enabled),
because the ADF4350 charge pump is unused. Set DB9, R4 to
0 for divided VCO output on RFOUTB+. Enable RFOUTB+
(auxiliary out). This signal is fed to the ADF4153 over the
coax cable.
2. Initialize the ADF4153 (as per the data sheet) to accept the
VCO output frequency as the RF input frequency. Note
that the band select switch is internal; therefore, an external
switch to remove the PLL VTUNE is not required.
3. When the ADF4153 achieves lock, the ADF4350 counter
reset to 1 (DB3, R2) must be activated. Not activating the
counter reset degrades spur performance. Additionally, all
ADF4350 synthesizer blocks can be powered down using
the test mode bit (DB10, R5).
Frequency Update
1. Program DB10, R5 to 0 to reactivate the ADF4350 synthesizer
blocks.
2. Program DB3, R2 of the ADF4350 to 0 to deactivate the
counter reset because these counters are required for band
select.
3. Program the ADF4350 and ADF4153 N-counter registers
as appropriate for the new frequency.
4. When the ADF4153 achieves lock, the ADF4350 counter
reset (DB3, R2) can be activated. Additionally all synthesizer
blocks can be powered down using the test mode bit
(DB10, R5).
5. Repeat Step 1 to Step 4 as required for new frequencies.
The software screen captures shown in Figure 5 and Figure 6 show
the software windows for 26 MHz REFIN (ADF4350) and 13 MHz
PFD (ADF4153).
After setting up the equipment, use standard RF test methods to
measure the spectral purity of the output signal.
CN-0232
Figure 5. ADF4350 Software Window
Figure 6. ADF4153 Software Window
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