CN-0232 Datasheet, PDF (1/6 Pages) Analog Devices – Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and an External PLL Circuit

Circuit Note
CN-0232
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
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Devices Connected/Referenced
ADF4350
Fractional-N PLL Synthesizer with
Integrated VCO
ADF4153 Fractional-N PLL Frequency Synthesizer
Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and
an External PLL Circuit
EVALUATION AND DESIGN SUPPORT
Circuit Evaluation Boards
ADF4350 Evaluation Board (EVAL-ADF4350EB2Z)
ADF4153 Evaluation Board (EVAL-ADF4153EBZ1)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
3.3V V_VCO
3.3V VDD
CIRCUIT FUNCTION AND BENEFITS
The circuit shown in Figure 1 uses the ADF4350 synthesizer with
an integrated VCO and an external PLL to minimize spurious
outputs by isolating the PLL synthesizer circuitry from the VCO
circuit.
LOCK
DETECT
V_VCO
REFERENCE
TCXO
26MHz
16 17
1nF 1nF
V_VCO
29 REFIN
51Ω
1 CLK
2 DATA
3 LE
28 10 4 26 6 32
30
25
MUXOUT LD
RF_OUTB+ 14
RF_OUTB– 15
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
VCO
V_VCO
4.7kΩ
22 R_SET
COUNTERS
RF_OUTA– 13
RF_OUTA+ ¹²
ADF4350
V_{TUNE 20}
CP_OUT 7
CPGND SD_GND AGND
8
31
9
A_GNDVCO
11 18 21
SW 5
DGND TEMP V_COM V_REF
27
19
23 24
51Ω 51Ω
1nF
1nF
51Ω 51Ω
1nF
1nF
VCO
TUNING
VOLTAGE
RFOUTA+
51Ω
RFOUTB+
51Ω
10pF
3.3V VDD
0.1µF 10pF
0.1µF 10pF
0.1µF
1nF 1nF
7
AV_DD
15
DV_DD
16
10
14
V_P
SDV_DD MUXOUT
8 REF_IN
11 CLK
12 DATA
13 LE
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP 2
LOOP FILTER
360Ω
100nF
22nF
4.7nF
4.7kΩ
1 R_SET
CPGND
COUNTERS
ADF4153
AGND DGND
RF_INA 6
RF_INB 5
200Ω
100pF
100pF
3
4
9
RF IN
51Ω
51Ω
Figure 1. ADF4153 PLL Connected to ADF4350 (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. 0
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