ADAU1702 Datasheet, PDF (5/52 Pages) Analog Devices – SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs

ADAU1702
REGULATOR
Table 6. Regulator¹
Parameter
DVDD Voltage
Min
Typ
1.7
1.8
1 _{Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.}
Max
1.84
Unit
V
DIGITAL TIMING SPECIFICATIONS
Table 7. Digital Timing¹
Parameter
MASTER CLOCK
tMP
tMP
tMP
tMP
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
tLOS
tLOH
tTS
tSODS
tSODM
SPI PORT
fCCLK
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I²C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tBFT
Limit
TMIN
TMAX
Unit
Description
36
244 ns
48
366 ns
73
488 ns
291 1953 ns
MCLK period, 512 fS mode.
MCLK period, 384 fS mode.
MCLK period, 256 fS mode.
MCLK period, 64 fS mode.
40
ns
INPUT_BCLK low pulse width.
40
ns
INPUT_BCLK high pulse width.
10
ns
INPUT_LRCLK setup. Time to INPUT_BCLK rising.
10
ns
INPUT_LRCLK hold. Time from INPUT_BCLK rising.
10
ns
SDATA_INx setup. Time to BCLK_IN rising.
10
ns
SDATA_INx hold. Time from BCLK_IN rising.
10
ns
OUTPUT_LRCLK setup in slave mode.
10
ns
OUTPUT_LRCLK hold in slave mode.
5
ns
OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew.
40
ns
SDATA_OUTx delay. Time from OUTPUT_BCLK falling in slave mode.
40
ns
SDATA_OUTx delay. Time from OUTPUT_BCLK falling in master mode.
6.25 MHz CCLK frequency.
80
ns
CCLK pulse width low.
80
ns
CCLK pulse width high.
0
ns
CLATCH setup. Time to CCLK rising.
100
ns
CLATCH hold. Time from CCLK rising.
80
ns
CLATCH pulse width high.
0
ns
CDATA setup. Time to CCLK rising.
80
ns
CDATA hold. Time from CCLK rising.
101 ns
COUT delay. Time from CCLK falling.
400 kHz SCL frequency.
0.6
μs
SCL high.
1.3
μs
SCL low.
0.6
μs
Setup time, relevant for repeated start condition.
0.6
μs
Hold time. After this period, the first clock is generated.
100
ns
Data setup time.
300 ns
SCL rise time.
300 ns
SCL fall time.
300 ns
SDA rise time.
300 ns
SDA fall time.
0.6
Bus-free time. Time between stop and start.
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