ADAU1702 Datasheet, PDF (38/52 Pages) Analog Devices – SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs

ADAU1702
2076 (0x081C)—DSP CORE CONTROL REGISTER
Table 46.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
RSVD RSVD GD1 GD0 RSVD RSVD RSVD AACW GPCW IFCW IST
D4 D3 D2
ADM DAM CR
D1 D0 Default
SR1 SR0 0x0000
Table 47. DSP Core Control Register
Bit Name
Description
GD [1:0]
Sets debounce time of multipurpose pins that are set as GPIO inputs.
GPIO Debounce Control
GD [1:0] Time (ms)
00
20
01
40
10
10
11
5
AACW
Auxiliary ADC Data
Registers Control Port
Write Mode
Setting this bit allows data to be written directly to the auxiliary ADC data registers (2057 to 2060) from the
control port. When this bit is set, the auxiliary ADC data registers ignores the settings on the multipurpose pins.
GPCW
When this bit is set, the GPIO pin setting register (2056) can be written to directly from the control port and
GPIO Pin Setting Register this register ignores the input settings on the multipurpose pins.
Control Port Write Mode
IFCW
Interface Registers
Control Port Write Mode
When this bit is set, data can be written directly to the interface registers (2048 to 2055) from the control port.
In that state, the interface registers are not written from the SigmaDSP program.
IST
Initiate Safeload Transfer
Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit is automatically cleared when
the operation is complete. There are five safeload register pairs (address/data); only those registers that have
been written since the last safeload event are transferred to the parameter RAM.
ADM
Mute ADCs
This bit mutes the output of the ADCs. The bit defaults to 0 and is active low; therefore, it must be set to 1 to
transmit audio signals from the ADCs.
DAM
Mute DACs
This bit mutes the output of the DACs. The bit defaults to 0 and is active low; therefore, it must be set to 1 to
transmit audio signals from the DACs.
CR
Clear Internal
Registers to 0
This bit defaults to 0 and is active low. It must be set to 1 for a signal to pass through the SigmaDSP core.
SR [1:0]
Sample Rate
These bits set the number of DSP instructions for every sample and the sample rate at which the ADAU1702
operates. At the default setting of 1×, there are 512 instructions per audio sample. This setting should be used
with sample rates such as 48 kHz and 44.1 kHz.
At the 2× setting, the number of instructions per frame is halved to 256 and the ADCs and DACs nominally run
at a 96 kHz sample rate.
At the 4× setting, there are 128 instructions per cycle and the converters run at a 192 kHz sample rate.
SR [1:0] Setting
00
1× (512 instructions)
01
2× (256 instructions)
10
4× (128 instructions)
11
Reserved
Rev. 0 | Page 38 of 52