AD9915 Datasheet, PDF (5/48 Pages) Analog Devices – 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC

Data Sheet
AD9915
AC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, T_A = 25°C, R_SET = 3.3 kΩ, I_OUT =
20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 2.
Parameter
REF CLK INPUT
REF CLK Multiplier Bypassed
Input Frequency Range
Duty Cycle
Minimum Differential Input Level
System Clock (SYSCLK) PLL Enabled
VCO Frequency Range
VCO Gain (K_V)
Maximum PFD Rate
CLOCK DRIVERS
SYNC_CLK Output Driver
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
SYNC_OUT Output Driver
Frequency Range
Duty Cycle
Rise Time (20% to 80%)
Fall Time (20% to 80%)
DAC OUTPUT CHARACTERISTICS
Output Frequency Range (1^st Nyquist
Zone)
Output Resistance
Min
500
45
632
2400
45
33
0
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Wideband SFDR
−10
AVDD −
0.50
122.5 MHz Output
305.3 MHz Output
497.5 MHz Output
978.2 MHz Output
Narrow-Band SFDR
122.5 MHz Output
305.3 MHz Output
497.5 MHz Output
978.2 MHz Output
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Minimum Master Reset time
24
Maximum DAC Calibration Time (t_CAL)
Maximum PLL Calibration Time (t_{REF_CLK})
Maximum Profile Toggle Rate
Typ Max
Unit
2500
55
2500
60
125
MHz
%
mV p-p
MHz
MHz/V
MHz
Test Conditions/Comments
Input frequency range
Maximum f_OUT is 0.4 × f_SYSCLK
Equivalent to 316 mV swing on each leg
156
MHz
50 55
%
650
ps
6.5
MHz
66
%
1350
ps
1670
ps
10 pF load
CFR2 register, Bit 9 = 1
10 pF load
10 pF load
1250
MHz
50
Ω
5
pF
20.48
mA
+10
% FS
0.6
μA
AVDD + V
0.50
−67
dBc
−66
dBc
−59
dBc
−60
dBc
−95
dBc
−95
dBc
−95
dBc
−92
dBc
Single-ended (each pin internally terminated to
AVDD (3.3V))
Range depends on DAC R_SET resistor
See the Typical Performance Characteristics
section
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
See the Typical Performance Characteristics
section
±500 kHz
±500 kHz
±500 kHz
±500 kHz
45
250
152
16
8
1
ns
ns
SYSCLK cycles
µs
ms
ms
SYNC_CLK period
Power-down mode loses DAC/PLL calibration
settings
Must recalibrate DAC/PLL
f_CAL = f_SYSCLK/384 USR0 register, Bit 6 = 0; see the
DAC Calibration Output section for formula
PFD rate = 25 MHz
PFD rate = 50 MHz
Rev. A | Page 5 of 48