AD9510 Datasheet, PDF (5/60 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

AD9510
Parameter
NOISE CHARACTERISTICS
In-Band Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit
PLL DIGITAL LOCK DETECT WINDOW⁴
Required to Lock
(Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
To Unlock After Lock (Hysteresis)⁴
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Min Typ
Max Unit Test Conditions/Comments
−172
−156
−149
−142
−218 +
10 × log (fPFD)
3.5
7.5
3.5
7
15
11
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
The synthesizer phase noise floor is
estimated by measuring the in-band
phase noise at the output of the VCO and
subtracting 20logN (where N is the
N divider value).
Approximation of the PFD/CP phase noise
floor (in the flat region) inside the PLL loop
bandwidth. When running closed loop this
phase noise is gained up by 20 × log(N)³.
Signal available at STATUS pin
when selected by 08h<5:2>.
Selected by Register ODh.
ns
<5> = 1b.
ns
<5> = 0b.
ns
<5> = 0b.
Selected by Register ODh.
ns
<5> = 1b.
ns
<5> = 0b.
ns
<5> = 0b.
1 _{REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.}
2 _{CLK2 is electrically identical to CLK1; the distribution-only input can be used as differential or single-ended input (see the Clock Inputs section).}
3 _{Example: −218 + 10 × log(fPFD) + 20 × log(N) should give the values for the in-band noise at the VCO output.}
4 _{For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.}
CLOCK INPUTS
Table 2.
Parameter
CLOCK INPUTS (CLK1, CLK2)¹
Input Frequency
Input Sensitivity
Input Level
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Min Typ Max Unit
Test Conditions/Comments
0
1.6
150²
2³
1.5 1.6 1.7
1.3
1.8
150
4.0 4.8 5.6
2
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Jitter performance can be improved with higher slew
rates (greater swing).
Larger swings turn on the protection diodes and can
degrade jitter performance.
Self-biased; enables ac coupling.
With 200 mV p-p signal applied; dc coupled.
CLK2 ac-coupled; CLK2B ac-bypassed to RF ground.
Self-biased.
1 _{CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.}
2 _{With a 50 Ω termination, this is −12.5 dBm.}
3 _{With a 50 Ω termination, this is +10 dBm.}
Rev. A | Page 5 of 60