AD9510 Datasheet, PDF (49/60 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

AD9510
REGISTER MAP DESCRIPTION
Table 24 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle
brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 24 describes the
functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 23.
Table 24. AD9510 Register Descriptions
Reg.
Addr.
(Hex) Bit(s) Name
Description
Serial Control Port Any changes to this register takes effect immediately. Register 5Ah<0> Update Registers does not
Configuration
have to be written.
00 <3:0>
Not Used.
00 <4> Long Instruction When this bit is set (1), the instruction phase is 16 bits. When clear (0), the instruction phase is 8 bits.
The default, and only, mode for this part is long instruction (Default = 1b).
00 <5> Soft Reset
When this bit is set (1), the chip executes a soft reset, restoring default values to the internal registers,
except for this register, 00h. This bit is not self-clearing. A clear (0) has to be written to it in order
to clear it.
00 <6> LSB First
When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register addressing
increments. If this bit is clear (0), data is oriented as MSB first and register addressing decrements.
(Default = 0b, MSB first.)
00 <7> SDO Inactive
(Bidirectional
Mode)
When set (1), the SDO pin is tri-state and all read data goes to the SDIO pin. When clear (0), the SDO is
active (unidirectional mode). (Default = 0b.)
Not Used
01 <7:0>
Not Used
02 <7:0>
Not Used
03 <7:0>
Not Used
PLL Settings
04 <5:0> A Counter
6-Bit A Counter <5:0>
04 <7:6>
Not Used
05 <4:0> B Counter MSBs 13-Bit B Counter (MSB) <12:8>
05 <7:5>
Not Used
06 <7:0> B Counter LSBs 13-Bit B Counter (LSB) <7:0>
07 <1:0>
Not Used
07 <2> LOR Enable
1 = Enables the Loss-of-Reference (LOR) Function; (Default = 0b)
07 <4:3>
Not Used
07 <6:5> LOR Initial Lock
Detect Delay
LOR Initial Lock Detect Delay. Once a lock detect is indicated, this is the number of phase frequency
detector (PFD) cycles that occur prior to turning on the LOR monitor.
<6>
<5>
LOR Initial Lock Detect Delay
0
0
3 PFD Cycles (Default)
0
1
6 PFD Cycles
1
0
12 PFD Cycles
1
1
24 PFD Cycles
07 <7>
Not Used
08 <1:0> Charge Pump
Mode
<1>
<0>
Charge Pump Mode
0
0
Tri-Stated (Default)
0
1
Pump-Up
1
0
Pump-Down
1
1
Normal Operation
Rev. A | Page 49 of 60