AD7938-6 Datasheet, PDF (5/32 Pages) Analog Devices – 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer

AD7938-6
TIMING SPECIFICATIONS¹
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; FCLKIN = 10MHz, FSAMPLE = 625 kSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter
fCLKIN
tQUIET
Limit at TMIN, TMAX
AD7938-6 Unit
50
kHz min
10
MHz max
30
ns min
Description
Minimum time between end of read and start of next conversion, i.e., time from
when the data bus goes into three-state until the next falling edge of CONVST.
t1
10
ns min
CONVST Pulse Width.
t2
15
ns min
CONVST Falling Edge to CLKIN Falling Edge Setup Time.
t3
50
ns min
CLKIN Falling Edge to BUSY Rising Edge.
t4
0
ns min
CS to WR Setup Time.
t5
0
ns min
CS to WR Hold Time.
t6
10
ns min
WR Pulse Width.
t7
10
ns min
Data Setup Time before WR.
t8
10
ns min
Data Hold after WR.
t9
10
ns min
New Data Valid before Falling Edge of BUSY.
t10
0
ns min
CS to RD Setup Time.
t11
0
ns min
CS to RD Hold Time.
t12
30
ns min
RD Pulse Width.
t132
30
ns max
Data Access Time after RD.
t143
3
ns min
Bus Relinquish Time after RD.
50
ns max
Bus Relinquish Time after RD.
t15
0
ns min
HBEN to RD Setup Time.
t16
0
ns min
HBEN to RD Hold Time.
t17
10
ns min
Minimum Time between Reads/Writes.
t18
0
ns min
HBEN to WR Setup Time.
t19
10
ns min
HBEN to WR Hold Time.
t20
40
ns max
CLKIN Falling Edge to BUSY Falling Edge.
t21
15.7
ns min
CLKIN Low Pulse Width.
t22
7.8
ns min
CLKIN High Pulse Width.
1 _{Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.}
All timing specifications given above are with a 25 pF load capacitance (see Figure 35, Figure 36, Figure 37, and Figure 38).
2 _{The time required for the output to cross 0.4 V or 2.4 V.}
3 _{t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or}
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
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