AD7938-6 Datasheet, PDF (15/32 Pages) Analog Devices – 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer

AD7938-6
CIRCUIT INFORMATION
The AD7938-6 is a fast, 8-channel, 12-bit, single-supply,
successive approximation analog-to-digital converter. The
part can operate from a 2.7 V to 5.25 V power supply and
features throughput rates up to 625 kSPS.
The AD7938-6 provides the user with an on-chip track-and-
hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP
or TQFP package.
The AD7938-6 has eight analog input channels that can
be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo-differential pairs, or seven
pseudo-differential inputs with respect to one common
input. There is an on-chip user-programmable channel
sequencer that allows the user to select a sequence of channels
through which the ADC can progress and cycle with each
consecutive falling edge of CONVST.
The analog input range for the AD7938-6 is 0 to VREF or 0 to
2 × VREF depending on the status of the RANGE bit in the
control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7938-6 provides flexible power management options
to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0,
in the control register.
CONVERTER OPERATION
The AD7938-6 is a successive approximation ADC based
around two capacitive DACs. Figure 14 and Figure 15 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises of control logic, a SAR,
and two capacitive DACs. Both figures show the operation of
the ADC in differential/pseudo-differential mode. Single-ended
mode operation is similar but VIN− is internally tied to AGND.
In acquisition phase, SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor arrays acquire the differential signal on
the input.
V_IN+
V_IN–
B
C_S
A
SW1
A
SW2
B
C_S
V_REF
CAPACITIVE
DAC
SW3
CONTROL
LOGIC
COMPARATOR
CAPACITIVE
DAC
Figure 14. ADC Acquisition Phase
When the ADC starts a conversion (Figure 15), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once
the conversion begins. The control logic and the charge
redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to
bring the comparator back into a balanced condition. When
the comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the VIN+ and the VIN− pins
must match; otherwise, the two inputs have different settling
times, which result in errors.
V_IN+
V_IN–
B
C_S
A
SW1
A
SW2
B
C_S
V_REF
CAPACITIVE
DAC
SW3
CONTROL
LOGIC
COMPARATOR
CAPACITIVE
DAC
Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7938-6 is either straight binary
or twos complement, depending on the status of the CODING
bit in the control register. The designed code transitions occur
at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on) and the
LSB size is VREF/4096 . The ideal transfer characteristics of the
AD7938-6 for both straight binary and twos complement
output coding are shown in Figure 16 and Figure 17,
respectively.
111...111
111...110
111...000
011...111
1 LSB = V_REF/4096
000...010
000...001
000...000
0V
1 LSB
ANALOG INPUT
+V_REF–1 LSB
NOTE: V_REF IS EITHER V_REF OR 2 × V_REF
Figure 16. AD7938-6 Ideal Transfer Characteristic
with Straight Binary Output Coding
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