AD7729ARZ Datasheet, PDF(5/16 Page) Analog Devices – Dual Sigma-Delta ADC with Auxiliary DAC

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AD7729ARZ Datasheet, PDF (5/16 Pages) Analog Devices – Dual Sigma-Delta ADC with Auxiliary DAC

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TIMING DIAGRAMS

Figure 2. Clock Timing

100â®A IOL

TO OUTPUT PIN

15pF

100â®A IOH

+2.1V

Figure 3. Load Circuit for Timing Specifications

AD7729

MCLK

*ASCLK

*ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY

(MCLK/4 SHOWN HERE).

Figure 4. ASCLK

MCLK

*BSCLK

*BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY

(MCLK/4 SHOWN HERE).

Figure 5. BSCLK

ASE (I)

ASCLK (O) THREE-STATE

t 10

ASDIFS (I)

t 11

ASDI (I)

THREE-STATE

t 12

ASDOFS (O)

THREE-STATE

ASDO (O)

NOTE

I = INPUT, O = OUTPUT

t 11

t10

t 13

t17

t 16

t 14

t 15

Figure 6. Auxiliary Serial Port ASPORT

BSE (I)

THREE-STATE

BSCLK (O)

t 18

BSDIFS (I)

t 19

BSDI (I)

THREE-STATE

t 20

BSDOFS (O)

THREE-STATE

BSDO (O)

NOTE

I = INPUT, O = OUTPUT

t19

t18

t 21

t 22

t 23

t25

t 24

Figure 7. Baseband Serial Port BSPORT

REV. 0

â5â

▷