AD7729ARZ Datasheet, PDF(14/16 Page) Analog Devices – Dual Sigma-Delta ADC with Auxiliary DAC

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AD7729ARZ Datasheet, PDF (14/16 Pages) Analog Devices – Dual Sigma-Delta ADC with Auxiliary DAC

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AD7729

Table VIII. Baseband Control Register B (BCRB)

Bit

BCRB0

BCRB1

BCRB2

BCRB3

BCRB4

BCRB5

BCRB6

BCRB7

BCRB8

BCRB9

Name

Reserved

RxSPORTSEL

Reserved

Function

REFOUT Use.

Reference Low Power.

Selects the SPORT

that will provide

RxDATA when RxON is

asserted. When set to 0,

the BSPORT is selected

and, when set to 1, the

ASPORT is selected.

Table IX. Auxiliary Control Register A (ACRA)

Bit

ACRA0

ACRA1

ACRA2

ACRA3

ACRA4

ACRA5

ACRA6

ACRA7

ACRA8

ACRA9

Name

Reserved

AUXDACON

Reserved

Function

Power On for Auxiliary DAC

Table X. Auxiliary Control Register B (ACRB)

Bit

ACRB0

ACRB1

ACRB2

ACRB3

ACRB4

ACRB5

ACRB6

ACRB7

ACRB8

ACRB9

Name

ARESET

Reserved

Function

Resets the Auxiliary Converter

Writing Over the Baseband (or Auxiliary) SPORT

Writing to and reading from registers via the SPORT involves

the transfer of 16 bit words, 10 bits of data and 6 bits of address

(with the exception of the Rx data). The frame format is as

shown in Figure 19, Bit 15 being the first input bit of the frame.

The destination of the 10-bit data is determined by the 6-bit

destination address as indicated in Figure 19. Note that some

registers are read only and, hence, cannot be written to.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A5 A4 A3 A2 A1 A0

Figure 19. Write Operation Frame Format

Reading Over the Baseband (or Auxiliary) SPORT

To read the contents of a register, the address of the appropriate

BRDADDR. The time interval between writing to the read

address register and the frame synchronization signal becoming

active equals 4 MCLK cycles. The read address register is

6 bits wide and Bits D11 to D6 of the input frame are used to

write to this register, Bits D12 to D15 being donât cares, as

shown in Figure 20. The frame format for reading is identical to

that for writing i.e., 10 bits of data followed by 6 address bits

corresponding to the source address of the data (with the excep-

tion of the Rx data).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X X X X RA5 RA4 RA3 RA2 RA1 RA0 0 0 1 0 1 0

Figure 20. Writing to the Read Address Register

(BRDADDR Shown Here)

Receiving RxDATA

The Rx ADC is activated by taking either the RxON bit or the

RxON pin high. In this mode, Rx data is automatically output

on the SDO pin of the SPORT at a word rate of 270 kHz for

each of I and Q, after a delay of T1 + T2 + T3 (see Figure 16).

The data format is I followed by Q. The AD7729 will output

16 bits of data, the 15-bit I or Q word, which is in twos comple-

ment format, and a flag bit. This flag bit (LSB) distinguishes

between the I and Q words, the bit being at 0 when the word

being output is an I word while this bit is at 1 when the output

is a Q word.

When RxON is taken high, the serial clock will have a frequency

of 13 MHz, irrespective of the value in the clock rate register.

When the AD7729 is ready to output Rx data, an output frame

synchronization signal is generated and the Rx data is automati-

cally output on the SDO pin, an I and Q word being output

every 48 MCLK cycles (see Figure 17). Data can be output on

the ASPORT or the BSPORT, bit RxSPORTSEL in control

received on one SPORT only, the user cannot interchange from

one SPORT to the other.

MICROPROCESSOR INTERFACING

The AD7729 has a standard serial interface which allows the

user to interface the part to several DSPs. In all cases, the

AD7729 operates as the master with the DSP acting as the

slave. The AD7729 provides its own serial clock to clock the

serial data/control information to/from the DSP.

AD7721-to-ADSP-21xx Interface

Figure 21 shows the AD7729 interface to the ADSP-21xx. For

the ADSP-21xx, the bits in the serial port control register

should be set up as TFSR = RFSR = 1 (a frame sync is needed

for each transfer), SLEN = 15 (16-bit word length), TFSW =

RFSW = 0 (normal framing), INVTFS = INVRFS = 0 (active

high frame sync signals), IRFS = 0 (external RFS), ITFS = 1

(internal TFS) and ISCLK = 0 (external serial clock).

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