AD5399 Datasheet, PDF (5/12 Pages) Analog Devices – Twos Complement, Dual 12-Bit DAC with Internal REF and Fast Settling Time

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5399
CLK 1
10 CS
SDI 2 _AD5399 9 ^VTP
DGND 3 TOP VIEW 8 V_DD
V_OUTB 4 ^{(Not to Scale)} 7 AGND
V_OUTA 5
6 ^V_BZ
Figure 3. MSOP-10 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
CLK
Serial Clock Input. Positive edge triggered.
2
SDI
Serial Data Input. MSB first format.
3
DGND
Digital Ground.
4
VOUTB
DAC B Voltage Output (A0 = Logic 1).
5
VOUTA
DAC A Voltage Output (A0 = Logic 0).
6
VBZ
2 V, Virtual Bipolar Zero (Active Output).
7
AGND
Analog Ground.
8
VDD
Positive Power Supply. Specified for operation at 5 V.
9
VTP
Connect to VDD. Reserved for factory testing.
10
CS
Chip Select (Frame Sync Input). Allows clock and data to shift into the shift register when CS goes from high to low.
After the 16^th clock pulse, it is not necessary to bring CS high to shift the data to the output. However, CS should be
brought high any time after the 16th clock positive edge in order to allow the next programming cycle.
Table 5. Serial Data-Word Format
ADDR
B15
B14
B13
B12
A0
X
SD
0
MSB
DATA
B11
B10
D11
D10
… B3
B2
B1
B0
… D3
D2
D1
D0
LSB
A0
X
SD
0
D0–D11
Address Bit. Logic low selects DAC A and logic high selects DAC B.
Both channels are shut down when the SD bit is high. However, the A0 bit must be at the same state for shutdown
activation and deactivation. See the Shutdown Function section.
Don’t Care.
Shutdown Bit. Logic high puts both DAC outputs and VBZ into high impedance. A0 bit must be at the same state for
shutdown activation and deactivation.
B12 must be 0.
Data Bits.
Rev. D | Page 5 of 12