AD5122A Datasheet, PDF (5/32 Pages) Analog Devices – The AD5122A/AD5142A are available in a compact, 16-lead, 3 mm × 3 mm LFCSP and a 16-lead TSSOP.

Data Sheet
AD5122A/AD5142A
Parameter
DYNAMIC CHARACTERISTICS⁹
Bandwidth
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
Crosstalk (CW1/CW2)
Analog Crosstalk
Endurance¹⁰
Data Retention¹¹
Symbol
BW
THD
eN_WB
tS
CT
CTA
Test Conditions/Comments Min
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
VDD/VSS = ±2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
TA = 25°C
100
Typ¹ Max
3
0.43
−80
−90
7
20
2
12
10
25
−90
1
50
Unit
MHz
MHz
dB
dB
nV/√Hz
nV/√Hz
µs
µs
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
1 _{Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.}
2 _{Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper}
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 _{Guaranteed by design and characterization, not subject to production test.}
4 _{INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits}
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 _{Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground}
referenced bipolar signal adjustment.
6 _{Different from operating current; supply current for EEPROM program lasts approximately 30 ms.}
7 _{Different from operating current; supply current for EEPROM read lasts approximately 20 µs.}
8 _{PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).}
9 _{All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V.}
10 _{Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.}
11 _{Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,}
derates with junction temperature in the Flash/EE memory.
Rev. A | Page 5 of 32