AD9690_17 Datasheet, PDF (49/79 Pages) Analog Devices – Analog-to-Digital Converter

AD9690
Data Sheet
DDC EXAMPLE CONFIGURATIONS
Table 23 describes the register settings for multiple DDC example configurations.
Table 23. DDC Example Configurations
Chip
Chip
DDC
Application Decimation Input
Layer
Ratio
Type
DDC
Output
Type
One DDC 2
Real
Complex
Two DDCs 4
Real
Real
Two DDCs 4
Real
Complex
Two DDCs 8
Real
Real
Bandwidth
per DDC¹
38.5% × fS
9.63% × fS
19.25% × fS
4.81% × fS
No. of Virtual
Converters
Required
2
2
4
2
Register Settings²
Register 0x200 = 0x01 (one DDC; I/Q selected)
Register 0x201 = 0x01 (chip decimate by 2)
Register 0x310 = 0x83 (complex mixer; 0 dB gain; variable IF;
complex outputs; HB1 filter)
Register 0x311 = 0x00 (default)
Register 0x331 = 0x00 (default)
Register 0x314, Register 0x315, Register x0320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x200 = 0x22 (two DDCs; I only selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x49 (real mixer; 6 dB gain;
variable IF; real output; HB3 + HB2 + HB1 filters)
Register 0x311 = 0x00 (default)
Register 0x331 = 0x00 (default)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x200 = 0x02 (two DDCs; I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x40 (real mixer; 6 dB gain;
variable IF; complex output; HB2+HB1 filters)
Register 0x311 = 0x00 (default)
Register 0x331 = 0x00 (default)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x200 = 0x22 (two DDCs; I only selected)
Register 0x201 = 0x03 (chip decimate by 8)
Register 0x310, Register 0x330 = 0x4A (real mixer; 6 dB gain;
variable IF; real output; HB4+HB3+HB2+HB1 filters)
Register 0x311 = 0x00 (default)
Register 0x331 = 0x00 (default)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
1 _{fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection.}
2 _{The NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed, to ensure the proper}
operation of the NCO. See the NCO Synchronization section for more information.
Rev. B | Page 48 of 78