AD9524BCPZ Datasheet, PDF (49/56 Pages) Analog Devices – Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

Data Sheet
AD9524
Table 50. PLL2 Loop Filter Control
Address Bits Bit Name
0x0F5
[7:6] Pole 2 resistor (RPOLE2)
[5:3] Zero resistor (RZERO)
[2:0] Pole 1 capacitor (CPOLE1)
0x0F6
[7:1] Reserved
0
Bypass internal RZERO
resistor
Description
Bit 7
Bit 6
RPOLE2
(Ω)
0
0
900
0
1
450
1
0
300
1
1
225
Bit 5
Bit 4
Bit 3
RZERO
(Ω)
0
0
0
3250
0
0
1
2750
0
1
0
2250
0
1
1
2100
1
0
0
3000
1
0
1
2500
1
1
0
2000
1
1
1
1850
Bit 2
Bit 1
Bit 0
CPOLE1
(pF)
0
0
0
0
0
0
1
8
0
1
0
16
0
1
1
24
1
0
0
24
1
0
1
32
1
1
0
40
1
1
1
48
Reserved.
Bypasses the internal RZERO resistor (RZERO = 0 Ω). Requires the use of a series external zero resistor.
This bit is the MSB of the loop filter control register (Address 0x0F5 and Address 0x0F6).
Rev. E | Page 49 of 56