|
AD6653 Datasheet, PDF (49/80 Pages) Analog Devices – IF Diversity Receiver | |||
|
◁ |
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0xFF, see Application Note AN-877, Interfacing to
High Speed ADCs via SPI, at www.analog.com.
SYNC Control (Register 0x100)
Bit 7âSignal Monitor Sync Enable
Bit 7 enables the sync pulse from the external sync input to the
signal monitor block. The sync signal is passed when Bit 7 and
Bit 0 are high. This is continuous sync mode.
Bit 6âHalf-Band Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the half-
band sync enable bit (Register 0x100, Bit 5) are high, Bit 6 allows
the NCO32 to synchronize following the first sync pulse it receives
and ignore the rest. If Bit 6 is set, Bit 5 of Register 0x100 resets
after this sync occurs.
Bit 5âHalf-Band Sync Enable
Bit 5 gates the sync pulse to the half-band filter. When Bit 5
is set high, the sync signal causes the half-band to resynchro-
nize, starting at the half-band decimation phase selected in
Register 0x103, Bit 3. This sync is active only when the master
sync enable bit (Register 0x100, Bit 0) is high. This is continuous
sync mode.
Bit 4âNCO32 Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the
NCO32 sync enable bit (Register 0x100, Bit 3) are high, Bit 4
allows the NCO32 to sync following the first sync pulse it receives
and ignores the rest. Bit 3 of Register 0x100 resets after a sync
occurs if Bit 4 is set.
Bit 3âNCO32 Sync Enable
Bit 3 gates the sync pulse to the 32-bit NCO. When this bit is set
high, the sync signal causes the NCO to resynchronize, starting
at the NCO phase offset value. This sync is active only when the
master sync enable bit (Register 0x100, Bit 0) is high. This is
continuous sync mode.
Bit 2âClock Divider Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the clock
divider sync enable bit (Register 0x100, Bit 1) are high, Bit 2
allows the clock divider to synchronize following the first sync
pulse it receives and ignore the rest. Bit 1 of Register 0x100
resets after it synchronizes.
Bit 1âClock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is passed when Bit 1 and Bit 0 are high. This is continuous
sync mode.
Bit 0âMaster Sync Enable
Bit 0 must be high to enable any of the sync functions.
AD6653
fS/8 Output Mix Control (Register 0x101)
Bits[7:6]âReserved
Bits[5:4]âfS/8 Start State
Bit 5 and Bit 4 set the starting phase of the fS/8 output mix.
Bits[3:2]âReserved
Bit 1âfS/8 Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the fS/8
sync enable bit (Register 0x101, Bit 0) are high, Bit 1 allows the
fS/8 output mix to synchronize following the first sync pulse it
receives and ignore the rest. Bit 0 of Register 0x100 resets after it
synchronizes.
Bit 0âfS/8 Sync Enable
Bit 0 gates the sync pulse to the fS/8 output mix. This sync is
active only when the master sync enable bit (Register 0x100,
Bit 0) is high. This is continuous sync mode.
FIR Filter and Output Mode Control (Register 0x102)
Bits[7:4]âReserved
Bit 3âFIR Gain
When Bit 3 is set high, the FIR filter path, if enabled, has a gain
of 1. When Bit 3 set low, the FIR filter path has a gain of 2.
Bit 2âfS/8 Output Mix Disable
Bit 2 disables the fS/8 output mix when enabled. Bit 2 should be
set along with Bit 1 to enable complex output mode.
Bit 1âComplex Output Mode Enable
Setting Bit 1 high enables complex output mode.
Bit 0âFIR Filter Enable
When set high, Bit 0 enables the FIR filter. When Bit 0 is
cleared, the FIR filter is bypassed and shut down for power
savings.
Digital Filter Control (Register 0x103)
Bits[7:4]âReserved
Bit 3âHalf-Band Decimation Phase
When set high, Bit 3 uses the alternate phase of the decimating
half-band filter.
Bit 2âSpectral Reversal
Bit 2 enables the spectral reversal feature of the half-band filter.
Bit 1âHigh-Pass/Low-Pass Select
Bit 1 enables the high-pass mode of the half-band filter when
set high. Setting this bit low enables the low-pass mode (default).
Bit 0âReserved
Bit 0 reads back as a 1.
Rev. 0 | Page 49 of 80
|
▷ |