AD6653 Datasheet, PDF (1/80 Pages) Analog Devices – IF Diversity Receiver

IF Diversity Receiver
AD6653
FEATURES
SNR = 70.8 dBc (71.8 dBFS) in a 32.7 MHz BW at
70 MHz @ 150 MSPS
SFDR = 83 dBc to 70 MHz @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
Integrated dual-channel ADC
Sample rates up to 150 MSPS
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC)
32-bit, complex, numerically controlled oscillator (NCO)
Decimating half-band filter and FIR filter
Supports real and complex output modes
Fast attack/threshold detect bits
Composite signal monitor
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
PRODUCT HIGHLIGHTS
1. Integrated dual, 12-bit, 125 MSPS/150 MSPS ADC.
2. Integrated wideband decimation filter and 32-bit
complex NCO.
3. Fast overrange detect and signal monitor with serial output.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Flexible output modes, including independent CMOS,
interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
6. SYNC input allows synchronization of multiple devices.
7. 3-bit SPI port for register programming and register readback.
AVDD
VIN+A
VIN–A
SHA
FUNCTIONAL BLOCK DIAGRAM
FD[0:3]A
DVDD
FD BITS/THRESHOLD
DETECT
ADC
I
LP/HP
DECIMATING
HB FILTER +
Q
FIR
DRVDD
AD6653
D11A
D0A
VREF
SENSE
CML
RBIAS
REF
SELECT
VIN–B
VIN+B
SHA
SIGNAL
MONITOR
ADC
32-BIT
TUNING
NCO
Q
LP/HP
DECIMATING
HB FILTER +
I
FIR
f_ADC/8
NCO
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
DCO
GENERATION
PROGRAMMING DATA
MULTI-CHIP
SYNC
FD BITS/THRESHOLD SIGNAL MONITOR
DETECT
DATA
SIGNAL MONITOR
INTERFACE
SPI
CLK+
CLK–
DCOA
DCOB
D11B
D0B
AGND SYNC
FD[0:3]B
SMI SMI SMI
SDIO/ SCLK/ CSB
SDFS SCLK/ SDO/
DCS DFS
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.
DRGND
Figure 1.
Rev. 0
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