ADSP-BF534 Datasheet, PDF (47/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF534/ADSP-BF536/ADSP-BF537
10/100 Ethernet MAC Controller Timing
Table 34 through Table 39 and Figure 29 through Figure 34
describe the 10/100 Ethernet MAC controller operations. This
feature is only available on the ADSP-BF536 and ADSP-BF537
processors. For more information, see Table 1 on Page 3.
Table 34. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter¹
t_ERXCLKF
ERxCLK Frequency (f_SCLK = SCLK Frequency)
t_ERXCLKW
ERxCLK Width (t_ERxCLK = ERxCLK Period)
t_ERXCLKIS
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
t_ERXCLKIH
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
1 _{MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.}
Table 35. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter¹
t_ETF
ETxCLK Frequency (f_SCLK = SCLK Frequency)
t_ETXCLKW
ETxCLK Width (t_ETxCLK = ETxCLK Period)
t_ETXCLKOV
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
t_ETXCLKOH
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)
1 _{MII outputs synchronous to ETxCLK are ETxD3–0.}
Table 36. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter¹
t_EREFCLKF
REF_CLK Frequency (f_SCLK = SCLK Frequency)
t_EREFCLKW
EREF_CLK Width (t_EREFCLK = EREFCLK Period)
t_EREFCLKIS
Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)
t_EREFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)
1 _{RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.}
Table 37. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter¹
t_EREFCLKOV
t_EREFCLKOH
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
1 _{RMII outputs synchronous to RMII REF_CLK are ETxD1–0.}
Min
None
t_ERxCLK × 35%
7.5
7.5
Max
25 MHz + 1%
f_SCLK + 1%
t_ERxCLK × 65%
Min
None
t_ETxCLK × 35%
0
Max
25 MHz + 1%
f_SCLK + 1%
t_ETxCLK × 65%
20
Min
None
t_EREFCLK × 35%
4
2
Max
50 MHz + 1%
2 × f_SCLK + 1%
t_EREFCLK × 65%
Min
Max
7.5
2
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
Rev. B | Page 47 of 68 | July 2006