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ADSP-BF534 Datasheet, PDF (28/68 Pages) Analog Devices – Blackfin Embedded Processor | |||
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ADSP-BF534/ADSP-BF536/ADSP-BF537
Asynchronous Memory Read Cycle Timing
Table 18. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
tSDAT
DATA15â0 Setup Before CLKOUT
tHDAT
DATA15â0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT 1
1 Output pins include AMS3â0, ABE1â0, ADDR19â1, AOE, ARE.
CLKOUT
AMSx
SETUP
2 CYCLES
tDO
PROGRAMMED READ ACCESS
4 CYCLES
Min
Max
Unit
2.1
ns
0.8
ns
4.0
ns
0.0
ns
6.0
ns
0.8
ns
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
tHO
ABE1â0
ADDR19â1
AOE
ARE
ARDY
DATA15â0
BE, ADDRESS
tDO
tSARDY
tHARDY
tHO
tHARDY
tSARDY
Figure 10. Asynchronous Memory Read Cycle Timing
tSDAT
READ
tHDAT
Rev. B | Page 28 of 68 | July 2006
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