ADSP-2195 Datasheet, PDF (46/68 Pages) Analog Devices – DSP Microcomputer

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ADSP-2195
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Serial Peripheral Interface (SPI) Port—Master Timing
Table 20 and Figure 23 describe SPI port master operations.
Table 20. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter Description
Min
Switching Characteristics
t_SDSCIM
SPIxSEL low to first SCLK edge (x=0 or 1)
t_SPICHM
Serial clock high period
t_SPICLM
Serial clock low period
t_SPICLK
Serial clock period
t_HDSM
Last SCLK edge to SPIxSEL high (x=0 or 1)
t_SPITDM
Sequential transfer delay
t_DDSPID
SCLK edge to data out valid (data out delay)
t_HDSPID
SCLK edge to data out invalid (data out hold)
Timing Requirements
t_SSPID
t_HSPID
Data input valid to SCLK edge (data input setup)
SCLK sampling edge to data input invalid
2t_HCLK
2t_HCLK
2t_HCLK
4t_HCLK
2t_HCLK
2t_HCLK
0
0
1.6
1.6
September 2001
Max
Unit
ns
ns
ns
ns
ns
ns
6
ns
5
ns
ns
ns
46
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrA
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.