ADSP-BF533SBBC-500 Datasheet, PDF (45/64 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 45
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point V_MEAS is 0.95 V for
V_DDEXT (nominal) = 1.8 V or 1.5 V for V_DDEXT (nominal) = 2.5 V/
3.3 V.
INPUT
OR
OUTPUT
V_MEAS
V_MEAS
Figure 45. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time t_ENA is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 46.
The time t_{ENA_MEASURED} is the interval, from when the reference
signal switches, to when the output voltage reaches V_TRIP(high)
or V_TRIP (low).
For V_DDEXT (nominal) = 1.8 V—V_TRIP (high) is 1.3 V and V_TRIP
(low) is 0.7 V.
For V_DDEXT (nominal) = 2.5 V/3.3 V—V_TRIP (high) is 2.0 V and
V_TRIP (low) is 1.0 V.
Time t_TRIP is the interval from when the output starts driving to
when the output reaches the V_TRIP (high) or V_TRIP (low) trip
voltage.
Time t_ENA is calculated as shown in the equation:
t_ENA = t_{ENA_MEASURED} – t_TRIP
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t_DIS is the
difference between t_{DIS_MEASURED} and t_DECAY as shown on the left
side of Figure 45.
t_DIS = t_{DIS_MEASURED} – t_DECAY
The time for the voltage on the bus to decay by V is dependent
on the capacitive load C_L and the load current I_I. This decay time
can be approximated by the equation:
t_DECAY = C_LV  I_L
The time t_DECAY is calculated with test loads C_L and I_L, and with
V equal to 0.1 V for V_DDEXT (nominal) = 1.8 V or 0.5 V for
V_DDEXT (nominal) = 2.5 V/3.3 V.
The time t_{DIS_MEASURED} is the interval from when the reference
signal switches, to when the output voltage decays V from the
measured output high or output low voltage.
t_DIS
V_OH
(MEASURED)
V_OL
(MEASURED)
REFERENCE
SIGNAL
t_{DIS_MEASURED}
t_ENA
V_OH (MEASURED) ؊ ⌬V
V_OL (MEASURED) + ⌬V
t_DECAY
t_{ENA_MEASURED}
V_OH(MEASURED)
V_TRIP(HIGH)
V_TRIP(LOW)
V_OL(MEASURED)
t_TRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Figure 46. Output Enable/Disable
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t_DECAY using the equation given above. Choose V
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. C_L is
the total bus capacitance (per data line), and I_L is the total leak-
age or three-state current (per data line). The hold time is t_DECAY
plus the various output disable times as specified in the Timing
Specifications on Page 27 (for example t_DSDAT for an SDRAM
write cycle as shown in SDRAM Interface Timing on Page 30).
Rev. I | Page 45 of 64 | August 2013