ADSP-BF533SBBC-500 Datasheet, PDF (41/64 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533
Timer Clock Timing
Table 35 and Figure 30 describe timer clock timing.
Table 35. Timer Clock Timing
Parameter
Switching Characteristic
t_TODP
Timer Output Update Delay After PPI_CLK High
Min
Max
Unit
12
ns
PPI_CLK
TMRx OUTPUT
t_TODP
Figure 30. Timer Clock Timing
Timer Cycle Timing
Table 36 and Figure 31 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of f_SCLK/2 MHz.
Table 36. Timer Cycle Timing
Parameter
V_DDEXT = 1.8 V
Min
Max
V_DDEXT = 2.5 V/3.3 V
Min
Max
Unit
Timing Characteristics
t_WL Timer Pulse Width Low¹
t_WH Timer Pulse Width High¹
t_TIS Timer Input Setup Time Before CLKOUT Low²
t_TIH Timer Input Hold Time After CLKOUT Low²
Switching Characteristics
t_HTO Timer Pulse Width Output
t_TOD Timer Output Update Delay After CLKOUT High
1 × t_SCLK
1 × t_SCLK
ns
1 × t_SCLK
1 × t_SCLK
ns
8.0
6.5
ns
1.5
1.5
ns
1 × t_SCLK (2³²â€“1) × t_SCLK 1 × t_SCLK (2³²â€“1) × t_SCLK ns
7.5
6.5
ns
1 _{The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.}
2 _{Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.}
CLKOUT
TMRx OUTPUT
TMRx INPUT
t_TOD
t_TIS
t_TIH
t_HTO
t_WH,t_WL
Figure 31. Timer PWM_OUT Cycle Timing
Rev. I | Page 41 of 64 | August 2013