AD9121 Datasheet, PDF (45/61 Pages) Analog Devices – TxDAC+ Digital-to-Analog Converter

AD9121
Data Sheet
DAC INPUT CLOCK CONFIGURATIONS
The AD9121 DAC sampling clock (DACCLK) can be sourced
directly or by clock multiplying. Clock multiplying uses the
on-chip phase-locked loop (PLL), which accepts a reference clock
operating at a submultiple of the desired DACCLK rate, most
commonly the data input frequency. The PLL then multiplies
the reference clock up to the desired DACCLK frequency, which
can then be used to generate all the internal clocks required by
the DAC. The clock multiplier provides a high quality clock that
meets the performance requirements of most applications. Using
the on-chip clock multiplier eliminates the need to generate and
distribute the high speed DACCLK.
The second mode bypasses the clock multiplier circuitry and
allows the DACCLK to be sourced directly to the DAC core.
This mode enables the user to source a very high quality clock
directly to the DAC core. Sourcing the DACCLK directly through
the REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may
be necessary in demanding applications that require the lowest
possible DAC output noise, particularly when directly synthesizing
signals above 150 MHz.
DRIVING THE DACCLK AND REFCLK INPUTS
The differential DACCLK and REFCLK inputs share similar
clock receiver input circuitry. Figure 62 shows a simplified circuit
diagram of the inputs. The on-chip clock receiver has a differential
input impedance of about 10 kΩ. It is self-biased to a common-
mode voltage of about 1.25 V. The inputs can be driven by
direct coupling differential PECL or LVDS drivers. The inputs
can also be ac-coupled if the driving source cannot meet the
input compliance voltage of the receiver.
DACCLKP,
REFCLKP
5kΩ
1.25V
5kΩ
DACCLKN,
REFCLKN
Figure 62. Clock Receiver Input Simplified Equivalent Circuit
The minimum input drive level to either of the clock inputs is
100 mV p-p differential. The optimal performance is achieved
when the clock input signal is between 800 mV p-p differential
and 1.6 V p-p differential. Whether using the on-chip clock
multiplier or sourcing the DACCLK directly, it is necessary that
the input clock signal to the device have low jitter and fast edge
rates to optimize the DAC noise performance.
DIRECT CLOCKING
Direct clocking with a low noise clock produces the lowest noise
spectral density at the DAC outputs. To select the differential
CLK inputs as the source for the DAC sampling clock, set the
PLL enable bit (Register 0x0A, Bit 7) to 0. This powers down the
internal PLL clock multiplier and selects the input from the
DACCLKP and DACCLKN pins as the source for the internal
DAC sampling clock.
The device also has duty cycle correction circuitry and differ-
ential input level correction circuitry. Enabling these circuits can
provide improved performance in some cases. The control bits
for these functions are in Register 0x08 (see Table 11).
CLOCK MULTIPLICATION
The on-chip PLL clock multiplication circuit can be used to gen-
erate the DAC sampling clock from a lower frequency reference
clock. When the PLL enable bit (Register 0x0A, Bit 7) is set to 1,
the clock multiplication circuit generates the DAC sampling clock
from the lower rate REFCLK input. The functional diagram of
the clock multiplier is shown in Figure 63.
The clock multiplication circuit operates such that the VCO
outputs a frequency, f_VCO, equal to the REFCLK input signal
frequency multiplied by N1 × N0.
f_VCO = f_REFCLK × (N1 × N0)
The DAC sampling clock frequency, f_DACCLK, is equal to
f_DACCLK = f_REFCLK × N1
The output frequency of the VCO must be chosen to keep f_VCO
in the optimal operating range of 1.0 GHz to 2.1 GHz. The
frequency of the reference clock and the values of N1 and N0
must be chosen so that the desired DACCLK frequency can be
synthesized and the VCO output frequency is in the correct range.
REG 0x06[7:6]
PLL LOCK LOST
PLL LOCKED
REFCLKP/REFCLKN
(PIN 69 AND PIN 70)
PHASE
DETECTION
LOOP
FILTER
ADC
REG 0x0E[3:0]
VCO CONTROL
VOLTAGE
VCO
÷N1
REG 0x0D[1:0]
N1
÷N0
REG 0x0D[3:2]
N0
DACCLKP/DACCLKN
(PIN 2 AND PIN 3)
REG 0x0A[7]
PLL ENABLE
DACCLK
÷N2
REG 0x0D[7:6]
N2
PC_CLK
Figure 63. PLL Clock Multiplication Circuit
Rev. B | Page 44 of 60