AD9121 Datasheet, PDF (36/61 Pages) Analog Devices – TxDAC+ Digital-to-Analog Converter

Data Sheet
FRAME InitiatedAbsoluteFIFOReset
In FIFO rate synchronization mode, the write pointer of the FIFO
is reset in an absolute manner. The synchronization signal aligns
the internal clocks on the part to a common reference clock so
that the pipeline delay in the digital circuit stays the same during
power cycles. The synchronization signal is sampled by the DAC
clock in the AD9121. The edge of the DAC clock used to sample
the synchronization signal is selected by Bit 3 of Register 0x10.
The FRAME signal is used to reset the FIFO write pointer. In
the FIFO rate synchronization mode, the FIFO write pointer is
reset immediately after the FRAME signal is asserted high for at
least the time interval required to load complete data to the I
and Q DACs. The FIFO write pointer is reset to the value of the
FIFO Phase Offset[2:0] bits in Register 0x17. FIFO rate synchro-
nization is selected by setting Bit 6 of Register 0x10 to 0.
SYNC
FIFO READ RESET
READ
POINTER
0
1
2
3
4
5
6
7
0
1
2
3
FRAME
FIFO WRITE
RESET
FIFO PHASE OFFSET[2:0]
REG 0x17[2:0] = 101
WRITE
POINTER
6
5
6
7
0
1
2
3
4
5
6
7
Figure 48. FRAME Input vs. Write Pointer Value, FIFO Rate Mode
AD9121
Monitoringthe FIFO Status
The FIFO initialization and status can be read from Register 0x18.
This register provides information about the FIFO status and
whether the initialization was successful. The MSB of Register 0x18
is a FIFO warning flag that can optionally trigger a device IRQ.
This flag indicates that the FIFO is close to emptying (FIFO
level is 1) or overflowing (FIFO level is 7). In this case, data
may soon be corrupted, and action should be taken.
The FIFO data level can be read from Register 0x19 at any time.
The serial port reported FIFO data level is denoted as a 7-bit
thermometer code (Base 1 code) of the write counter state
relative to the absolute read counter being at 0. The optimum
FIFO data level of 4 is therefore reported as a value of 00001111
in the status register.
Note that, depending on the timing relationship between the
DCI and the main DACCLK, the FIFO level value can be off
by a ±1 count, that is, the readback of Register 0x19 can be
00011111 in the case of a +1 count and 00000111 in the case of
a −1 count. Therefore, it is important to keep the difference
between the read and write pointers to a value of at least 2.
Rev. B | Page 35 of 60