ADSP-BF536_15 Datasheet, PDF (43/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Peripheral Interface Port—Slave Timing
Table 35 and Figure 25 describe SPI port slave operations.
Table 35. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t_SPICHS
Serial Clock High Period
t_SPICLS
Serial Clock Low Period
t_SPICLK
Serial Clock Period
t_HDS
Last SCK Edge to SPISS Not Asserted
t_SPITDS
Sequential Transfer Delay
t_SDSCI
SPISS Assertion to First SCK Edge
t_SSPID
Data Input Valid to SCK Edge (Data Input Setup)
t_HSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
t_DSOE
t_DSDHI
t_DDSPID
t_HDSPID
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
Min
Max
2 × t_SCLK – 1.5
2 × t_SCLK – 1.5
4 × t_SCLK
2 × t_SCLK – 1.5
2 × t_SCLK – 1.5
2 × t_SCLK – 1.5
1.6
1.6
0
8
0
8
10
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
CPHA = 1
SPIxMOSI
(INPUT)
t_SDSCI
t_SPICLS
t_SPICHS
t_DSOE
t_DDSPID
t_HDSPID
t_SSPID
t_HSPID
t_DSOE
SPIxMISO
(OUTPUT)
CPHA = 0
SPIxMOSI
(INPUT)
t_HDSPID
t_SPICLK
t_DDSPID
t_HDS
t_SPITDS
t_DSDHI
t_DDSPID
t_SSPID
t_DSDHI
t_HSPID
Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. J | Page 43 of 68 | February 2014