ADSP-BF536_15 Datasheet, PDF (41/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 33. External Late Frame Sync
Parameter
Min
Switching Characteristics
t_DDTLFSE
t_DTENLFS
Data Delay from Late External TFSx or External RFSx with MCMEN = 1, MFD = 0^{1, 2}
Data Enable from Late FS or MCMEN = 1, MFD = 0^{1, 2}
0
1 _{MCMEN = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFS.}
2 _{If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.}
Max
10.0
Unit
ns
ns
EXTERNAL RFSx IN MULTI-CHANNEL MODE
DRIVE
EDGE
SAMPLE
EDGE
RSCLKx
DRIVE
EDGE
RFSx
DTx
t_DDTLFSE
t_DTENLFSE
LATE EXTERNAL TFSx
DRIVE
EDGE
TSCLKx
1ST BIT
SAMPLE
EDGE
DRIVE
EDGE
TFSx
t_DDTLFSE
DTx
1ST BIT
Figure 23. External Late Frame Sync
Rev. J | Page 41 of 68 | February 2014