AD9522-5 Datasheet, PDF (42/76 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator

AD9522-5
CHANNEL DIVIDER
OUTPUT CLOCKING
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
1
1
2
3
4
5
6
7
8
9 10 11 12 13 14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER
OUTPUT CLOCKING
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
Figure 39. SYNC Timing Pipeline Delay When the VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 40. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used
LVDS Output Drivers
The AD9522 output drivers can be configured as either an
LVDS differential output or as a pair of CMOS single-ended
outputs. The LVDS outputs allow for selectable output current
from ~1.75 mA to ~7 mA.
The LVDS output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVDS output can be individually
powered down to save power.
3.5mA
OUT
OUT
3.5mA
Figure 41. LVDS Output Simplified Equivalent Circuit with
3.5 mA Typical Current Source
Rev. 0 | Page 42 of 76