HMC1197LP7FE Datasheet, PDF (40/57 Pages) Hittite Microwave Corporation – Fixed Wireless or WLL

HMC1197LP7FE
v03.0314
Wideband Direct Quadrature Modulator
w/ Fractional-N PLL & VCO, 100 - 4000 MHz
2.9
Bit
[2:0]
[10:3]
[11]
[19:12]
[20]
[21]
[23:22]
2.10
Bit
[4:0]
[5]
[9:6]
[10]
[20:11]
[21]
[22]
[23]
Reg 07h Lock Detect Register DEFAULT 200844 h
Type
Name
R/W lkd_wincnt_max
R/W
R/W
R/W
Reserved
LD Enable
Reserved
R/W Lock Detect Training
R/W CSP Enable
R/W Reserved
Width
3
8
1
8
9
1
2
Default
4
8
1
0
0
1
0
Description
lock detect window
sets the number of consecutive counts of divided VCO that
must land inside the Lock Detect Window to declare LOCK
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65535
Reserved
0: LD disable
1: LD enable
Reserved
0 to 1 transition triggers the training. Lock Detect Training
is only required after changing Phase Detector frequency.
After changing PD frequency a toggle Reg 07h[20] from 0
to 1 retrains the Lock Detect.
Cycle Slip Prevention enable.
When enabled, if the phase error becomes larger than
approx 70% of the PFD period, the charge-pump gain is
increased by approx 6mA for the duration of the cycle..
Reserved
Reg 08h Analog EN Register DEFAULT 1BFFF h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Name
Width
5
GPO(General Purpose Output Pin
Enable)
1
Reserved
4
VCO Buffer and Prescaler
Bias Enable
1
Reserved
10
High Frequency Reference
1
SDO Output Level
1
Reserved
1
Default
31d
1d
15d
1d
55d
0
0d
0d
Description
Reserved
0 - Pin LD_SDO disabled
1 - and RegFh[7]=1 , Pin LD_SDO is always driven, this is
required for use of GPO port
1 - and RegFh[7]=0 LDO_SPI is off if chip address
not equal to ‘000’b, allowing a shared SPI with other
compatible parts
Reserved
0: VCO Buffer and Prescaler Bias Disable
1: VCO Buffer and Prescaler Bias Enable
Only applies to External VCO
Reserved
Program to 1 for XTAL > 200 MHz, 0 otherwise
Output Logic Level on LD/SDO pin
0: 1.8 V Logic Levels
1: DVDD3V Logic Level
Reserved
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