HMC1197LP7FE Datasheet, PDF (34/57 Pages) Hittite Microwave Corporation – Fixed Wireless or WLL

HMC1197LP7FE
v03.0314
Wideband Direct Quadrature Modulator
w/ Fractional-N PLL & VCO, 100 - 4000 MHz
1.7
1.8
1.8.1
Chip Identification
The chip id information may be read by reading the content of read only register, chip_ID in Reg 00h.
For HMC1197LP7FE, chip id is C7701Ah.
SERIAL PORT Overview
The SPI protocol has the following general features:
a. 3-bit chip address , enable the use of up to 8 devices connected to the serial bus
b. Simultaneous Write/Read during the SPI cycle
c. 5-bit address space
d. 3 wire for Write Only capability, 4 wire for Read/Write capability
Typical serial port operation can be run with SCLK at speeds up to 50 MHz.
Serial Port WRITE Operation
AVDD = DVDD = 3V, AGND = DGND = 0V
Table 13. SPI WRITE Timing Characteristics
Parameter
t₁
t₂
t₃
t₄
t₅
t₆
Conditions
SDI setup time to SCLK Rising Edge
SCLK Rising Edge to SDI hold time
SEN low duration
SEN high duration
SCLK 32 Rising Edge to SEN Rising Edge
Recovery Time
Max Serial port Clock Speed
Min.
3
3
10
10
10
10
Typ.
50
Max
Units
ns
ns
ns
ns
ns
ns
MHz
A typical WRITE cycle is shown in Figure 41.
a. The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK.
b. the slave (HMC1197LP7FE) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK
(25-29)
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32). Hittite
reserves chip address a2:a0 = 000 for HMC1197LP7FE.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
i. Master clears SEN to complete the WRITE cycle.
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