ADV612_15 Datasheet, PDF (40/46 Pages) Analog Devices – Closed Circuit TV Digital Video Codec

ADV611/ADV612
Host Interface (Indirect Address, Indirect Register Data and Interrupt Mask/Status) Register Timing
The diagrams in this section show transfer timing for host read and write accesses to all of the ADV611/ADV612’s direct registers,
except the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers
are slower than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct
register, see the Host Interface (Compressed Data) Register Timing section. Note that for accesses to the Indirect Address, Indirect
Register Data and Interrupt Mask/Status registers, your system MUST observe ACK and RD or WR assertion timing.
Table XXVI. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Read Timing Parameters
Parameter
Description
t_{RD_D_RDC}
t_{RD_D_PWA}
t_{RD_D_PWD}
t_{ADR_D_RDS}
t_{ADR_D_RDH}
t_{DATA_D_RDD}
t_{DATA_D_RDOH}
t_{RD_D_WRT}
t_{ACK_D_RDD}
t_{ACK_D_RDOH}
RD Signal, Direct Register, Read Cycle Time (at 27 MHz VCLK)
RD Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
RD Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Read Setup
ADR Bus, Direct Register, Read Hold
DATA Bus, Direct Register, Read Delay
DATA Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)
WR Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)
ACK Signal, Direct Register, Read Delayed (at 27 MHz VCLK)
ACK Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)
NOTES
1_{RD input must be asserted (low) until ACK is asserted (low).}
2_{Maximum tDATA_D_RDD varies with VCLK according to the formula: tDATA_D_RDD (MAX) = 4 (VCLK Period) +16.}
3_{During STATS_R deasserted (low) conditions, tDATA_D_RDD may be as long as 52 VCLK periods.}
4_{Minimum tRD_D_WRT varies with VCLK according to the formula: tRD_D_WRT (MIN) = 1.5 (VCLK Period) –4.1.}
5_{Maximum tACK_D_RDD varies with VCLK according to formula: tACK_D_RDD (MAX) = 7 (VCLK Period) +14.8.}
6_{During STATS_R deasserted (low) conditions, tACK_D_RDD may be as long as 52 VCLK periods.}
Min
N/A¹
N/A¹
5
2
2
N/A
26
48.7⁴
8.6
11
Max
N/A
N/A
N/A
N/A
N/A
171.6^{2, 3}
N/A
N/A
287.1^{5, 6}
N/A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(I) RD
(I) ADR, BE, CS
(O) DATA
t_{RD D PWA}
VALID
t_{ADR D RDS}
t_{DATA D RDD}
t_{RD D RDC}
t_{RD D PWD}
t_{ADR D RDH}
VALID
t_{DATA D RDOH}
VALID
VALID
(I) WR
t_{RD D WRT}
(O) ACK
t_{ACK D RDD}
t_{ACK D RDOH}
Figure 32. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing
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