ADSP-BF531_06 Datasheet, PDF (40/60 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF531/ADSP-BF532
Programmable Flags Cycle Timing
Table 27 and Figure 25 describe programmable flag operations.
Table 27. Programmable Flags Cycle Timing
Parameter
Timing Requirement
t_WFI
Flag Input Pulse Width
Switching Characteristic
t_DFO
Flag Output Delay from CLKOUT Low
CLKOUT
PF (OUTPUT)
PF (INPUT)
t_DFO
FLAG OUTPUT
t_WFI
FLAG INPUT
Figure 25. Programmable Flags Cycle Timing
V_DDEXT = 1.8 V V_DDEXT = 2.5 V/3.3 V
Min Max Min
Max Unit
t_SCLK + 1
t_SCLK + 1
ns
6
6
ns
Rev. D | Page 40 of 60 | August 2006