ADSP-BF531_06 Datasheet, PDF (33/60 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF531/ADSP-BF532
Table 23. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
t_DTENE
Data Enable Delay from External TSCLK¹
t_DDTTE
Data Disable Delay from External TSCLK¹
t_DTENI
Data Enable Delay from Internal TSCLK¹
t_DDTTI
Data Disable Delay from Internal TSCLK¹
1 _{Referenced to drive edge.}
Table 24. External Late Frame Sync
Parameter
Switching Characteristics
t_DDTLFSE Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0^{1, 2}
t_DTENLFS Data Enable from Late FS or MCE = 1, MFD = 0^1,2
1 _{MCE = 1, TFS enable and TFS valid follow tDTENLFS and t . DDTLFSE}
2 _{If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.}
V_DDEXT = 1.8 V V_DDEXT = 2.5 V/3.3 V
Min Max Min Max Unit
0
0
ns
10.0
10.0
ns
−2.0
−2.0
ns
3.0
3.0
ns
V_DDEXT = 1.8 V V_DDEXT = 2.5 V/3.3 V
Min Max Min Max
Unit
10.0
0
0
10.0
ns
ns
Rev. D | Page 33 of 60 | August 2006