AD9959BCPZ Datasheet, PDF (40/44 Pages) Analog Devices – 4-Channel, 500 MSPS DDS with 10-Bit DACs

AD9959
Bit Mnemonic
5
SYNC_CLK disable
4
DAC reference power-down
3:2 Open
1
Manual hardware sync
0
Manual software sync
Description
0 = the SYNC_CLK pin is active (default).
1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is
shut down. However, the synchronization circuitry remains active internally to maintain normal
device operation.
0 = DAC reference is enabled (default).
1 = DAC reference is powered down.
See the Synchronizing Multiple AD9959 Devices section for details.
0 = the manual hardware synchronization feature of multiple devices is inactive (default).
1 = the manual hardware synchronization feature of multiple devices is active.
0 = the manual software synchronization feature of multiple devices is inactive (default).
1 = the manual software synchronization feature of multiple devices is active. See the
Synchronizing Multiple AD9959 Devices section for details.
Function Register 2 (FR2)—Address 0x02
Two bytes are assigned to this register. The FR2 is used to control the various functions, features, and modes of the AD9959.
Table 33. Bit Descriptions for FR2
Bit Mnemonic
15 All channels autoclear sweep
accumulator
14 All channels clear
sweep accumulator
13 All channels autoclear phase
accumulator
12 All channels clear phase
accumulator
11:8 Open
7
Auto sync enable
6
Multidevice sync master enable
5
Multidevice sync status
4
Multidevice sync mask
3: 2 Open
1:0 System clock offset
Description
0 = a new delta word is applied to the input, as in normal operation, but not loaded into the
accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the sweep accumulator for one
cycle upon reception of the I/O_UPDATE sequence indicator on all four channels.
0 = the sweep accumulator functions as normal (default).
1 = the sweep accumulator memory elements for all four channels are asynchronously cleared.
0 = a new frequency tuning word is applied to the inputs of the phase accumulator, but not
loaded into the accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the phase accumulator for one
cycle upon receipt of the I/O update sequence indicator on all four channels.
0 = the phase accumulator functions as normal (default).
1 = the phase accumulator memory elements for all four channels are asynchronously cleared.
See the Synchronizing Multiple AD9959 Devices section for more details.
See the Synchronizing Multiple AD9959 Devices section for more details.
See the Synchronizing Multiple AD9959 Devices section for more details.
See the Synchronizing Multiple AD9959 Devices section for more details.
See the Synchronizing Multiple AD9959 Devices section for more details.
Rev. B | Page 40 of 44