AD9959BCPZ Datasheet, PDF (15/44 Pages) Analog Devices – 4-Channel, 500 MSPS DDS with 10-Bit DACs

AD9959
CLOCK
SOURCE
AD9510
CLOCK DISTRIBUTOR
WITH
DELAY EQUALIZATION
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
FPGA
DATA
SYNC_IN
SYNC_CLK
REF_CLK
SYNC_OUT
C1
S1
AD9959 ^A1
(MASTER)
CENTRAL
CONTROL
FPGA
DATA
SYNC_CLK
FPGA
DATA
SYNC_CLK
C2
S2
AD9959
A2
(SLAVE 1)
C3
S3
AD9959
A3
(SLAVE 2)
FPGA
DATA
SYNC_CLK
C4
S4
AD9959
(SLAVE 3)
A4
A_END
Figure 25. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC_CLK
REFCLK
CH0
CH1
AD9959
CH2
CH3
OPTICAL FIBER CHANNEL
WITH MULTIPLE DISCRETE
WAVELENGTHS
SPLITTER
WDM SIGNAL
WDM
SOURCE
AMP
CH0
INPUTS
AMP
AMP
CH1
ACOUSTIC OPTICAL
TUNABLE FILTER
CH2
AMP
CH3
OUTPUTS
CH0 CH1 CH2 CH3
SELECTABLE WAVELENGTH FROM EACH
CHANNEL VIA DDS TUNING AOTF
Figure 26. DDS Providing Stimulus for Acoustic Optical Tunable Filter
REFCLK
CH0
AD9959
CH1
–
ADCMP563
+
Figure 27. Agile Clock Source with Duty Cycle Control Using the Phase Offset Value in DDS to Change the DC Voltage to the Comparator
Rev. B | Page 15 of 44