UG-630 Datasheet, PDF (4/8 Pages) Analog Devices – Evaluation Board User

UG-630
header to accept a Tektronix active probe, or installing a
2-pin header to allow adjacent channels to temporarily be
shorted together.
7. A 0805 pad layout between the signal and ground where a
load capacitor or resistor can be installed.
8. Pads to the adjacent channels are provided to allow permanent
connection of adjacent channels. Inputs can be fanned out
to several channels, or inputs and outputs can be connected
together to allow signals to loopback.
Figure 2 shows many of the optional components installed, as well
as how jumpers can be used to temporarily connect channels.
This figure shows a signal connected to the first channel SMA
and then fanned out to the top three channels and monitored by
an active scope probe.
BYPASS ON THE PCB
Several positions and structures are provided to allow optimum
bypass of the evaluation board. Provision has been made for
optional surface-mount bulk capacitors to be installed near
1 SMA CONNECTOR PADS
Evaluation Board User Guide
the power connectors to compensate for long cables to the
power supply. Parallel bypass capacitors are installed near the
ADuM1441ARQZ and consist of a 0.1 µF capacitor for each
VDDxA on the top side and bottom side and a 0.1 µF capacitor
for each VDDxB on the bottom side of the board. It is best to use
the top side bypass positions if possible.
The PCB also implements a distributed capacitive bypass on the
PCB. This consists of power and ground planes closely spaced
on the inner layers of the PCB. This minimizes noise and the
transmission of EMI without using complex design features.
HIGH VOLTAGE CAPABILITY
This PCB is designed in adherence with 2500 V basic insulation
practices. High voltage testing beyond 2500 V is not recommended.
Appropriate care must be taken when using this evaluation board
at high voltages, and the PCB should not be relied on for safety
functions because it has not been high potential tested (also
known as hipot tested or dielectric withstanding voltage tested)
or certified for safety.
2 TERMINATION
2 × 100Ω
6 OPEN HOLES FOR
SOLDERED WIRES OR 200mil
TEKTRONIX HEADER,
GND/GND/SIGNAL
8 CONNECT TO
NEXT CHANNEL UP
8 CONNECT TO
NEXT CHANNEL DOWN
4 PULL-UP
5 2-PIN HEADER
PAD
GND/SIGNAL
3 CONNECT
TO SMA
7 PULL-DOWN
PAD
NOTES
1. THE NUMBERED COMPONENTS IN THIS FIGURE CORRESPOND
TO THE DESCRIPTIONS IN THE DATA I/O STRUCTURES SECTION.
Figure 3. Configuration and Monitoring Structures (Showing a Datapath from an External Connection to the DUT Pin)
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