UG-478 Datasheet, PDF (4/40 Pages) Analog Devices – Evaluation Board for the AD7176-2—24-Bit, 250 kSPS Sigma-Delta ADC with 20 μs Settling

UG-478
EVALUATION BOARD HARDWARE
DEVICE DESCRIPTION
The AD7176-2 is a low noise, fast settling, multiplexed, 2-/4-
channel (fully differential/pseudo differential) Σ-Δ ADC. The
AD7176-2 has a maximum channel-to-channel scan rate of
50 kSPS (20 µs) for fully settled data. The output data rates
range from 5 Hz to 250 kHz.
Complete specifications for the AD7176-2 are provided in the
product data sheet and should be consulted in conjunction with
this user guide when using the evaluation board. Full details
Evaluation Board User Guide
about the EVAL-SDP-CB1Z are available on the Analog
Devices, Inc., website.
HARDWARE LINK OPTIONS
The default link options are listed in Table 1. By default, the
board is configured to operate from the external bench top
power supply via Connector J4. The supply required for the
AD7176-2 comes from the on-board ADP1720 LDOs, which
generate their input voltage from J4.
Table 1. Default Link and Solder Link Options
Link No. Default Option Description
LK1
A
Connects the AVDD1 voltage to the power supply sequencer, ADM1185.
When AVDD1 equals 5 V, LK1 must be in Position A.
When AVDD1 equals 2.5 V, LK1 must be in Position B.
LK2
A
Selects the connector for the external 7 V to 9 V power supply.
In Position A, this link selects the external 7 V to 9 V power supply to come from Connector J4.
In Position B, this link selects the external 7 V to 9 V power supply to come from Connector J5.
LK5 to LK9 Inserted
Inserting LK5 to LK9 sets up the on-board noise test. In this mode, all inputs are shorted to the REFOUT pin.
SL1
A
Sets the voltage applied to the AVDD2 pin.
In Position A, this link sets the voltage applied to the AVDD2 pin to be the same voltage applied to the
AVDD1 pin.
In Position B, this link sets the voltage applied to the AVDD2 pin to be a 3.3 V supply from the ADP1720-3.3 (U10)
regulator or from an external voltage.
AVDD2 cannot be set to 3.3 V when AVDD1 equals 2.5 V and AVSS equals −2.5 V.
SL2
A
Sets the voltage applied to the AVDD1 pin.
In Position A, this link sets the voltage applied to the AVDD1 pin to be a 5 V supply from the ADP1720-5 (U7)
regulator or a 2.5 V supply from the ADP1720 (U4) regulator.
In Position B, this link sets the voltage applied to the AVDD1 pin to be supplied from an external voltage
source via Connector J9.
When AVDD1 equals 2.5 V, AVSS can be set to −2.5 V using an external supply connected to Connector J9. The
AVSS to AGND solder links must be removed when a split power supply is used.
SL3, SL7 A, A
With SL3 and SL7 in Position A, AVDD1 is supplied with 5 V from ADP1720-5 (U7) regulator.
With SL3 and SL7 in Position B, AVDD1 is supplied with 2.5 V from the ADP1720 (U4) regulator.
SL4
A
With this link in Position A, the AIN4 analog input on the AD7176-2 device is connected to Connector J8.
With this link in Position B, the AIN4 analog input is connected to the REFOUT pin of the AD7176-2.
With this link in Position C, the AIN4 analog input is connected to ground for use with four pseudo
differential inputs, if required.
SL5
B
With this link in Position A, the IOVDD supply is provided from an external source via Connector J9.
With this link in Position B, the 3.3 V supply is generated by the ADP1720-3.3 (U10) regulator.
The evaluation system operates with 3.3 V logic.
SL6
Not Inserted
Allows an external crystal or clock to be used as the clock source for the AD7176-2.
With SL6 not inserted, a crystal is connected to the AD7176-2.
With SL6 in Position B, an external clock source can be supplied to the ADC.
SL8
B
With this link in Position A, the AIN1 analog input on the AD7176-2 device is connected to Connector J8.
With this link in Position B, the analog input applied via Connector J8 is buffered using the AD8656 before
being applied to the AIN1 pin.
With this link in Position C, the analog input path includes the ADA4940-1 differential amplifier; therefore,
in conjunction with AIN0, a single-ended to differential driver is implemented.
With this link in Position D, AIN1 is connected to Header J10.
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