SSM2120 Datasheet, PDF (4/12 Pages) Analog Devices – Dynamic Range Processors/Dual VCA

SSM2120/SSM2122
TRIMMING THE VCAs
The control feedthrough (CFT) pins are optional control feed-
through null points. CFT nulling is usually required in applications
such as noise gating and downward expansion. If trimming is
not used, leave the CFT pins open.
Trim Procedure
1. Apply a 100 Hz sine wave to the control point attenuator.
The signal peaks should correspond to the control voltages
which induce the VCAs maximum intended gain and at least
30 dB of attenuation.
2. Adjust the 50 kΩ potentiometer for the minimum
feedthrough.
(Trimmed control feedthrough is typically well under 1 mV rms
when the maximum gain is unity using 36 kΩ input and output
resistors.)
Applications such as compressor/limiters typically do not require
control feedthrough trimming because the VCA operates at
unity-gain unless the signal is large enough to initiate gain
reduction. In this case the signal masks control feedthrough.
This trim is ineffective for voltage-controlled filter applications.
LEVEL DETECTION CIRCUITS
The SSM2120 contains two independent level detection
circuits. Each circuit contains a wide dynamic range full-wave
rectifier, logging circuit and a unipolar drive amplifier. These
circuits will accurately detect the input signal level over a
100 dB range from 30 nA to 3 mA peak-to-peak.
LEVEL DETECTOR THEORY OF OPERATION
Referring to the level detector block diagram of Figure 3, the
REC_IN input is an AC virtual ground. The next block imple-
ments the full-wave rectification of the input current. This
current is then fed into a logging transistor (Q₁) whose pair
transistor (Q₂) has a fixed collector current of I_REF. The LOG
AV output is then:
V _LOG
AV
=
kT
q

ln_
|_IIRIENF|
With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of I_IN.
(The unfiltered LOG AV output has broad flat plateaus with
sharp negative spikes at the zero crossing. This reduces the
“work” that the averaging capacitor must do, particularly at low
frequencies.)
Note: It is natural to assume that with the addition of the
averaging capacitor, the LOG AV output would become the
average of the log of the absolute value of I_IN. However, since the
capacitor forces an ac ground at the emitter of the output
transistor, the capacitor charging currents are proportional to
the antilog of the voltage at the base of the output transistor.
Since the base voltage of the output transistor is the log of the
absolute value of I_IN, the log and antilog terms cancel, so the
capacitor becomes a linear integrator with a charging current
directly proportional to the absolute value of the input current.
This effectively inverts the order of the averaging and logging
functions. The signal at the output therefore is the log of the
average of the absolute value of I_IN.
USING DETECTOR PINS REC_IN, LOG_AV, THRESH AND
CON_OUT
When applying signals to REC_IN (rectifier input) an input series
resistor should be followed by a low leakage blocking capacitor
since REC_IN has a dc voltage of approximately 2.1 V above
ground. Choose R_IN for a ± 1.5 mA peak signal. For ± 15 V
operation this corresponds to a value of 10 kΩ.
A 1.5 MΩ value of R_REF from log average to –15 V will establish
a 10 µA reference current in the logging transistor (Q₁). This
will bias the transistor in the middle of the detector’s dynamic
current range in dB to optimize dynamic range and accuracy.
The LOG AV outputs are buffered and amplified by unipolar
drive op amps. The 39 kΩ, 1 kΩ resistor network at the
THRESH pin provides a gain of 40.
An attenuator from the CON_OUT (control output) to the
appropriate VCA control port establishes the control sensitivity.
Use 200 Ω for the attenuator resistor to ground and choose
R_CON for the desired sensitivity. Care should be taken to minimize
capacitive loads on the control outputs CON_OUT. If long lines
or capacitive loads are present, it is best to connect the series
resistor R_CON as closely to the CON_OUT pin as possible.
DYNAMIC LEVEL DETECTOR CHARACTERISTICS
Figures 4 and 5 show the dynamic performance of the level
detector to a change in signal level. The input to the detector (not
shown) is a series of 500 ms tone bursts at 1 kHz in successive
10 dBV steps. The tone bursts start at a level of –60 dBV (with
R_IN = 10 k) and return to –60 dBV after each successive 10 dB
step. Tone bursts range from –60 dBV to +10 dBV. Figure 4
shows the logarithmic level detector output. The output of the
detector is 3 mV/dB at LOG AV and the amplifier gain is 40
which yields 120 mV/dB. Thus, the output at CON_OUT is seen
to increase by 1.2 V for each 10 dBV increase in input level.
1kΩ
39kΩ
R_IN
REC_IN
INPUT
2V
V+
THRESH
FULL
WAVE
RECTIFIER
|I_IN|
I_REF
Q2
Q1
CON_OUT
LOG AV
V–
R_CON
TO V_C
200Ω
C_AV
R_REF
V–
Figure 3. Level Detector
–4–
REV. C