EVAL-AD766XCB Datasheet, PDF (4/15 Pages) Analog Devices – Evaluation Board AD766X/AD767X

PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
Jumper Default position
Designation with the control
board ( Factory
settings)
JP13
A, U3 side
JP14
JP15
JP16
A, U3 side
A, U3 side
A, U3 side
JP17
A, U3 side
JP18
JP19
JP20
A, U3 side
not A
not A
TABLE II. JUMPER DESCRIPTION
Function
Selection of IMPULSE. When the button of the switch is close to J4 connector
( not A position ), the ADC uses the IMPULSE mode which is the mode with the
lowest power dissipation. With the AD7660, JP13 is a spare switch.
TEST1. For factory use only and it is pull down.
TEST0. For factory use only and it is pull down.
Selection of EXT/INT ( use of external or internal serial clock ). When the button of
the switch is close to J4 connector ( not A position ) and when the serial reading
mode is selected, the data are read with an external serial clock SCLK generated from
the master clock MCLK otherwise the data are read with the ADC serial clock. When
external serial clock reading mode is selected, MCLK has to be fast enough to be able
the read the data properly as explained in the AD766X data sheet. JP16 has no use in
parallel reading mode.
Selection of INVSYNC ( SYNC active level ). When the button of the switch is close
to J4 connector ( not A position ) and when the master serial reading mode is se
lected, the SYNC signal is active Low. JP17 has no use in parallel reading mode or
slave serial reading mode.
Selection of INVSCLK ( SCLK active edge ). When the button of the switch is close
to J4 connector ( not A position ) and when the serial reading mode is selected,
INVSCLK is high. JP18 has no use in parallel reading mode.
Selection of CNVST signal. When JP19 is in position A, the signal on J3 is used
otherwise the on-board CNVST generation is used. MCLK signal is used to generate
the on-board CNVST signal.
Selection of REF signal. When JP20 is in position A, the REF is buffered. When
JP20 is not in position A, the REF is not buffered.
Table III. EVAL-AD766XCB/AD767XCB Test Points
Test Point
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
Available Signal
DGND Digital ground
DGND Digital ground
SIG+ ADC Analog input
AGND Analog ground close to SIG+
REF ADC Reference input
BUSY ADC BUSY signal
R D ADC RD signal
CS
ADC CS signal
AGND Analog ground close to REF
CNVST ADC CNVST signal
F_SYNC MCLK divided by 2
OVDD ADC digital output supply
DVDD ADC digital core supply
VANA1 ADC analog supply
AGND Analog ground close to SIG-
SIG- ADC Analog input
Table IV. Component values Vs. Input ranges ( AD7660 )
Input range
± 10V
± 5V
0 to -5V
R1
R3
R6
R7
8k⍀ 1k⍀ 8k⍀ 10k⍀
8k⍀ 2k⍀ 6.67k⍀ 10k⍀
8k⍀ 8k⍀ 0⍀
none
Table V. Component values Vs. Input ranges ( AD7664 )
Input range
± 10V
± 5V
0 to -5V
R1
R3
R6
R7
2k⍀ 250⍀ 8k⍀ 10k⍀
2k⍀ 500⍀ 6.67k⍀ 10k⍀
1k⍀ 1k⍀ 0⍀
none
–4–
REV. PrK