EVAL-AD766XCB Datasheet, PDF (2/15 Pages) Analog Devices – Evaluation Board AD766X/AD767X

PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
OPERATING THE EVAL-AD766XCB/AD767XCB
The EVAL-AD766XCB/AD767XCB is a four-layer board
carefully laid out and tested to demonstrate the specific high
accuracy performance of the AD766X/AD767X. Figure 1
shows the schematics of the evaluation board. The layouts of
the board are given in :
Top side silk-screen - Figure 2
Top side layer - Figure 3
Ground layer - Figure 4
Shield layer - Figure 5
Bottom side layer - Figure 6
Bottom side silk-screen - Figure 7.
The EVAL-AD766XCB/AD767XCB is a flexible design that
enables the user to choose among many different board con-
figurations. A description of each selectable jumper/switch is
listed in Table II and the available test points are listed in
Table III. Note that the button of a switch in position A ( U3
side ) defines a low level.
The EVAL-AD766XCB/AD767XCB is configured in factory
with 0 to 2.5 V ADC input range for the AD7660, AD7664,
and AD7675/7676/7677 and +/-5V for the AD7663/7665/
7671; front-end amplifiers U6 and U7 set with a gain of +1,
powered through the EVAL-CONTROL BOARD, and the
on-board CNVST generation used.
On-board or external CNVST could be used. When an exter-
nal CNVST signal is applied, this signal should have very low
jitter and sharp edges to get the best noise performance of the
part. Meanwhile, it is recommended to use the on-board
CNVST generation which is done by dividing MCLK signal
(20MHZ) by the numbers shown in Table I, which are en-
tered in the software. Activity on BUSY pin of the ADC
turns on the LED.
Table I. CNVST GENERATION
Part
AD7660
Division Factor
200
Throughput Rate
100KSPS
AD7662/68 40
AD7663
80
AD7664/50 35
500KSPS
250KSPS
571KSPS
AD7665
35
571KSPS
tor P1. When slave serial reading mode of the
AD766X/AD767X is used, the external serial clock SCLK
applied to the ADC is at half the MCLK frequency.
Power Supplies and Grounding
The evaluation board ground plane is separated into two
sections: a plane for the digital interface circuitry and an ana-
log plane for the analog input and external reference
circuitry. To attain high resolution performance, the board
was designed to ensure that all digital ground return paths do
not cross the analog ground return paths.
The EVAL-AD766XCB/AD767XCB has three power supply
blocks: a single 5V supply VA (SJ1) for the AD766X/AD767X
and the reference voltage circuitry, a digital 5V supply VL (SJ2)
for the digital interface circuitry and the digital section of the
ADC, and a selectable +/-12V (with a possibility of +/-15V
with control Brd2) or +/-5V supply for the analog signal con-
ditioning circuitry (SJ3). All supplies are decoupled to ground
with 10 ␮F tantalum and 0.1 ␮F ceramic capacitors.
Analog Input Ranges
The analog front-end amplifier circuitry U6 and U7 allows
flexible configuration changes such as positive or negative
gain, input range scaling, filtering, addition of a DC compo-
nent, use of different op-amp and supplies.
Figure 1 shows the front end op-amp configuration used with
the AD7660/7663/7664/7665/7671/7675/7676/7677.
In some applications, it is desired to use a bipolar or wider
analog input range like, for instance, ± 10V, ± 5V, ± 2.5V, or
0 to +5V. For the AD76XX parts which do not have directly
those input ranges like the AD7660/7664/7675/7676/7677,
by simple modifications of the input driver circuitry of the
EVAL-AD766XCB/AD767XCB, bipolar and wider input
ranges can be used without any performance degradation.
Components values required and resulting full-scale ranges
are shown in table IV and table V.
In factory, the analog input of U6 is set at mid-scale
(R6=R7=590⍀) for the AD7660/7664/7675/7676/7677. For
AD7663/7665/7671, R7 is not connected to maintain the
input at 0V (mid-scale). This allows a transition noise test
without any other equipment. An FFT test can be done by
applying a very low distortion AC source.
AD7671
20
AD7675
200
AD7676
35
1MSPS
100KSPS
571KSPS
EVAL-CONTROL BOARD INTERFACE
The EVAL-AD766XCB/AD767XCB interfaces to the EVAL-
CONTROL BRD2 through the 96-way connector.
AD7677
20
1MSPS
RUNNING THE EVAL-AD766X/AD767XCB SOFTWARE
Conversion data is available at the output bus BD on U3, on
Software Description
the 40-pin connector P2, and on the 96-pin connector P3.
The EVAL-AD766XCB/AD767XCB comes with software for
Additionally, BD data is updated on the falling/rising edge of
analyzing the AD766X/AD767X. Through the EVAL-CON-
DBUSY and BBUSY on P3, low when BD data is valid are
TROL BRD2 one can perform a histogram to determine code
delayed from the BD data by about 20 ns to ease the inter-
transition noise, and Fast Fourier Transforms (FFT's) to
face. When either parallel or serial reading mode of the ADC determine the Signal-to-Noise Ratio (SNR), Signal-to-Noise-
is used, the data is available on this parallel bus. When serial
plus-Distortion (SNRD) and Total-Harmonic-Distortion
reading mode of the ADC is used, the serial interface signals
(THD). The front-end PC software has four screens as
of the ADC are buffered and available on the 20-pin connec- shown in Figure 8,9,10 and 11. Figure 8 is the Setup Screen
where input voltage range, sample rate, number of samples
are selected. Figure 9 is the Histogram Screen, which allows
the code distribution for DC input and computes the mean
– 2 –^{and standard deviation.}
REV. PrK