DAS1155_15 Datasheet, PDF (4/4 Pages) Analog Devices – 14 BIT 15 BIT LOW LEVEL DATA ACQUISITION SYSTEMS

begins, and all internallogie is reset. Once the conversion process
OFFSET CALIBRATION
is initiated, it cannot be retriggered until after the end of
conversIOn.
For 0 to + JOY unipolar range set the input voltage precisely to
+ 305f.lY for the DASI155 andf I53,LY for the DAS1156.
With this negative edge of the trigger pulsc thc MSB is set low
with the remaining digital outputs set 10 logic high state, and
the status line is set high and remains high thru the full conversion
cycle. During conversion each bit, starting with the MSB, is
sequentially switched low at the rising edge of the internal clock.
The internal DAC output is then compared to the analog input
Then adjust the zero potentiometcr until the converter is just on
the verge of switching from 00 00 to ()()---uOI.
For the -'-5V bipolar range set the input voltage precisely to
+ 305f.lY for the DAS 1155 and + 153fLY for the DAS 1156.
Adjust the zero potentiometer until the offset binary coded units
are just on the verge of switching from 00 00 10 00 01 and
and the bit decision is made. Each comparison lasts one clock
cycle with the complete 14-1l5-bit conversion taking 35f.ls/
the two's complement coded units are just on the verge of switching
from 10 00 to 10 0 I.
44f.ls maximum respectively for the DASI155/DASI156.
GAIN CALIBRATION
At this time, the STATUS line goes low signifving that the
Set the input voltage precisely \0 + 9.99909 (OASI155)/
conversion is complete. For bus applications, the digital output
+9.99954Y (DASI156) for the 0 to + IOY units, or +4.99909Y
can now be applied 10 the selected data bus bv enabling the
tri-state buffers with the HI-ENABLE and LO-ENABLE ter-
minals.
(DASI155)/ +4.99954V (DASI156) for :t 5V units. Note that
these values are I 1/2LSB less than nominal full scale. Adjust
the gain potentiometer until binary and offset binary coded
GAIN AND OFFSET ADJUSTMENTS
units are just on the verge of switching from 11 10 to I I---nl I
OBSOLETE The DASI155/DASI156 each are provided with internal gain
and offset adjustment potentiometers. Each potentiometer has
ample adjustment range so that gain and offset errors can be
trimmed to zero.
Since offset calibration is not affected by changes in gain cali-
bration, it should be performed first. Proper gain and offset
calibration require great care and the use of extremely sensitive
and accurate reference instruments. The voltage standard used
as a signal source must be very stable and be capable of being
set to within :t IIlOLSB of the desired value at any point within
its range.
The analog input values given in Tables I, II, III and in the
following Offset & Gain Calibration Section, are values that
should be present at the input to the internal ADc. The value
of the analog input will be affected by the gain of the input
jnstrumentation amplifier.(Example: For a full scale input of 0
and two's complement coded units are just on the verge of
switching from 011 10 to 011 11.
THROUGHPUT RATE
Throughput rates for the DASI155/DASI156 can be increased
by the use of the OVERLAP MODE, i.e. updating the input
while the ADC is making a conversion.
The guaranteed throughput rates are 25kHz ((I G = I, 20kHz
(ii. G = 1000 for the DASI155 and 20kHz (il G = I and 1000
for the DAS 1156. When the IA settling time is less than or
equal to the sum of SHA acquisition time and ADC conversion
time, 39f.ls, the DAS throughput rate equals 1/39f.ls or 25.6kHz.
When IA settling time is greater than 39f.ls (see Figure 5), the
DAS throughput rate becomes dependent upon the IA settling
time and equals its reciprocal.
DAS1l55/DAS1l56 INPUT/OUTPUT RELATIONSHIPS
The DASI155/DASI156 produces a true binary coded output
to + 5V, divide the 0 to + lOY range input values by 2 and set
when configured as a unipolar device. Configured as a bipolar
input gain to 2.)
device, it can produce either offset binary or two's complement
Analog Input
Oto + lOV Range
DASllSS
DASllS6
DASllSS
Digital Output
Binary C<>de
DASllS6
+9.99939V +9.99969V 11 III III III III
+ S.OOOOOV + S.OOOOOV I0 000 000 000 000
+ I.2S000V + I.2S000V 00 I00 000 000 000
+ 0.0006V + 0.0003V 00 000 000 000 00 I
+ O.OOOOV + O.OOOOV 00 000 000 000 000
III III III III III
100 000 000 000 000
001 000000 000 000
000 000 000 000 00 I
000 000 000 000 000
Table I. Nominal Unipolar/Output Relationships
output codes. The most significant bit (MSB) is used to obtain
the binary and offset binary code while the (MSB) is used to
obtain the two's complement code. Table I shows the unipolar
analog input/digital output DASI155/DASI156 relationships.
Tables II and III show the DASll55/DASll56 bipolar analog
input/digital output relationships respectively.
TRI-STATE DIGITAL OUTPUT
The digital outputs are provided in parallel format to the output
tri-state buffers. The output information can be applied to a
Analog Input
:!:SV Range
+4.99939V
+ 2.S0000V
+0.0006IV
+ O.OOOOOV
- S.OOOOOV
Digital Output
Offset Binary Code Two's Complement Code
Illl1111111111O11l111I1J1111
II 000 000 000 000 0 I 000 000 000 000
10000 000 000 001 00 000 000 000 001
I0 000 000 000 000 00 000 000 000 000
00 000 000 000 000 I0 000 000 000 000
data buss in either a one-byte or a two-byte format by using the
HI-ENABLE and La-ENABLE terminals. If the tri-state feature
is not required, normal digital outputs can be obtained by con-
necting the enable pins to ground.
POWER SUPPLY AND GROUNDING CONNECTIONS
Although the analog power ground and the digital ground are
connected in the DASIl55/DASIl56, care must still be taken to
Table II. DASl155 Bipolar Input/Output Relationships
provide proper grounding due to the high accuracy nature of
the devices. Though only general guidelines can be given, ground-
Analog Input
:!:SV Range
+ 4.99969V
+ 2.S0000V
+ 0.00030V
+ O.OOOOOV
- S.OOOOOV
Digital Output
Offset Binary Code Two's Complement Code
III III III III III
II 0 000 000 000 000
I00 000 000 000 00 I
I00 000 000 000 000
011111 III III III
0 I0 000 000 000 000
000 000 000 000 00 1
000 000 000 000 000
000 000 000 000 000 100 000 000 000 000
ing should be arranged in such a manner as to avoid ground
loops and to minimize the coupling of voltage drops (on the
high current carrying logic supply ground) to the sensitive analog
circuit sections. Analog and digital grounds should remain sepa-
rated on the PC board and terminated at the respective DAS II 55/
DASI156 terminals.
Table III. DASl156 Bipolar Input/Output Relationships
No power supply decoupling is required since, both the DASI155
and DAS 1156, contain high quality tantalum capacitors on each
of the power supply inputs to ground.
VOL. II, 15-20 DATA ACQUISITION SUBSYSTEMS
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