DAS1155_15 Datasheet, PDF (3/4 Pages) Analog Devices – 14 BIT 15 BIT LOW LEVEL DATA ACQUISITION SYSTEMS

Applyingthe DAS1155/DAS1156
REF OU1
CONNEC1 r-
: I 'g';.:~7~~R _L- ':;:~::
GAIN
AOJUS1
imbalance for the DASll55/DASIl56. Increasing the input gain
of the instrumentation amplifier increases the CMR. At Gain =
IVN, CMR is maintained greater than 80dB for source impedance
imbalance up to !Ok!!. Figure 4 illustrates the CMR vs. gain
'4- "8'T
A'"
CONVERTER
and frequency.
SETTLING TIME VS. GAIN
Illustrated in Figure 5 is the typical settling time vs. gain of the
instrumentation amplifier in the DAS1155/DAS1156. Settling
SIH CONTROL
times are specified to 0.003% FSR for gains I and 10, and to
0.01% FSR for gain to 1000 having an output step voltage of 10
Figure 2. Analog Input Block Diagram
volts. Settling time to 0.003% FSR for gains greater than 10 are
not shown because of the effects of voltage noise at the higher
gains.
The gain T.c., of the DAS1l55/DAS1l56, will be directly
35
OBSOLE_{E TE} ^{affected by the resistor used for RG' Using a high quality metal}
film resistor is recommended. Bipolar operation is obtained by
connecting the REF OUT and the BIPOLAR OFFSET terminals
together.
The output of the instrumentation amplifier drives the sample/hold
amplifier which has a gain of IVN. The sample/hold amplifier
holds the input signal at a constant level during the A/D conversion.
Acquisition times of 4J.Lsand 5J.Lsmaximum are provided re-
spectively by the DAS1l55 and DAS1l56. Full scale AID converter
input range is programmed for + IOV (unipolar) or:!: 5V (bipolar).
Therefore, the instrumentation amplifier gain must be set ac-
cordingly to obtain maximum usable resolution.
COMMON MODE REJECTION
CMR is dependent on source impedance imbalance, signal fre-
quency, and amplifier gain. CMR is specified having a :!:IOV
CMV and lkn source imbalance over a frequency range of dc to
500Hz. Figure 3 illustrates the typical CMR vs. source impedance
";. 30
, 25
"~
20~
'"
~ 15
::
~ 10
5
1
----
10
100
GAIN- VN
~-
1000
Figure 5. Typical Settling Time vs Gain
TIMING DIAGRAM
The timing diagram for the DASIl5S/DASIl56 is illustrated in
Figure 6. This figure includes the sample/hold amplifier charac-
teristics and assumes that the 'instrumentation amplifier is allowed
to settle during the previous conversion.
r-.. TRtGGERI
} J SIH CONTROl
IN^SIHPUT^+FS.--'- ^'
SIGNAL -FS
-:
,
,
110
!g 90
ex:
:u:; 80
70
------
60
1k
.- - _u_~--_.
10k
f = 60Hz
lOOk
£; ^+FS
- -i SIH OUTPUT_-._{FS -,}
'NTERNAL nnnn
nnn
CLOCI< J W W W ~T--I W W L-
roc~3S.' _{".' M}M_AA_XIIX_D;_A~_SI1'"
MSB==~LJ
s~
D'
---,--, ~~
BlTZ J U
U'
B_"I lT3_r:==~j _,, 8_II,
"
I
I
.
SOURCE IMBALANCE - "
Figure 3. CMR vs Gain and Source Imbalance DAS1155/
- - J ILSa FOBIfTt D1A4 51155I__-
_u _J BIT"
(LSa FOR DA511"'_--
1>U-1~ fU//#t1
s~,
DAS1156
NOTES
150
140
:::-
130
120
!g 110
, 100
ex:
u^{::; 90}
BO
10,
60,
50,
.....G - 1000
..:......
...........
/ = 10 ........
=1
I'
-....... ............
"'"
-...::::::
10'
- ^10-'
10'
f Hz
10'
--
,
10'
Figure 4. CMR vs Frequency DASl155/DASl156
.W& " Output Data Valid,
2. This Diagram assumes that tha Instrumentation
Amplifier
Is allowed suffICient time to settle before the SamplelHold
Amplifier Is placed in the Sample Mode. Instrumentation Amplifier
settling can take place during the AID Conversion process
for Ihe next conversion (see throughput ratel.
3. The SfH Control and Trigger are tied together. Pulse Width
must be 4..s (minll5..s (mini to allow the SfH Amplifier to acquire
the Input Signa"
Figure 6. DAS 1155/DAS 1156 Timing Diagram
The TRIGGER input and S/H CONTROL terminal can be tied
together requiring only one conversion control signal. When the
trigger pulse goes high, it places the sample/hold amplifier in
the sample mode allowing it to acquire the present input signal.
The trigger pulse must remain high for a minimum of 4I-Ls/5J.Ls,
for the DASII55/DASII56 respectivelY1 to insure accuracy is
attained. At the falling edge of the TRIGGER pulse, the sample/
hold amplifier is placed in the hold mode, the A/D conversion
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DA TA Ar.nlJ/SITlnN SUBSYSTEMS V.Q.L.JL 1Jj-19