DAS1151_15 Datasheet, PDF (4/4 Pages) Analog Devices – LOW LEVEL INPUT 12 BIT DATA ACQUISITION MODULES

GAIN AND OFFSET ADJUSTMENT PROCEDURE
TIMING
The "0" to "1" transition of the CONVERT COMMAND in-
put resets the MSB output to Logic "0" and the CLOCK
ADC
ANALOG INPUT
I DIGITAL OUTPUT
. +5V RANGE +1OVR.ANGET-BINARYCOOE-
+4.9988V
+9.99'~~1ITT1i1T1fiT~-"
+2.5000V
+5.0000V I 100000000000
STATUS, MSB, and BIT 2 through BIT 12 outputs to Logic
"1 ". Nothing further happens until the CONVERT COM-
MAND retUrns to Logic "0", at which time the conversion
proceeds.
+0.6250V
+0.0012V
+1.2500V
+0.0024V
001000000000
000000000001
With the MSB in the Logic "0" state, the internal digital-to-
+O.OOOOV
+O.OOOOV
000000000000
analog converter's (DI A) output is compared with the analog
.~.,~""--"
.input (SHA OUT). If the D/A output is less than the analog in-
m
Table 2. Nominal Unipolar Input-Output Relationships
put, the first "0" to "1" clock transition resets the MSB Logic
r--
CD
~~~~!OG
ADC
,I.~~UT-~
L"-~~~I2lliill\!;.Q
UTPUr
O'S
"1 ". If the D/ A output is greater than the analog input, the
MSB remains at Logic "0".
The first "0" to "1" clock transition also sets the BIT 2 out-
mI
mI
~
10
:!:2.5V
:!:5V
tl0V
OFFSET BINAR
EMENT _{put to Logic "0" and another comparison is made. This pro-}
()
RANGE _{.~~~._-~-~}
+2.4988V +4.9976V
+9.9951V
..~- CODE,....
111111111111
CODE
01 fiTillli 1111
cess continues through each successive bit until the BIT 12
+1.2500V
+0.0012V
+O.OOOOV
-2.5000V
+2.5000V
+0.0024V
+O.OOOOV
-5.0000V
+5.0000V
+0.0049V
+O.OOOOV
-10.0000V
110000000000
100000000001
100000000000
000000000000
0100000000000
0000000000001
0000000000000
1000000000000
Table 3. Nominal Bipolar Input-Output Relationships
OOFFSET CALIBRATION
For unipolar mode set the input voltage precisely to the value
B _{of 1LSB (see Table 2) and adjust the offset potentiometer}
until the converter is just on the verge of switching from
S _{000000000000 to 000000000001.}
O _{For bipolar mode set the input voltage precisely to zero volts.}
Adjust the offset potentiometer until the offset binary coded
L ^u _{units are just on the verge of switching from 011111111111 to}
E 100000000000 and two's complement coded units are just on
the verge of switching 111111111111 to 000000000000.
- ^TE GAIN CALIBRATION
(LSB) comparison is completed. At this time the STATUS out-
put returns to Logic "0" and the conversion cycle ends.
The SERIAL DATA output is of the non-retUrn-to-zero (NRZ)
type. The data is available, MSB first, 40ns after each of the
twelve "0" to "1" clock transitions.
JL ~g~~~~';,
CLOCK
J STATUS
L-
MSB~
~ BIT2
BIT 3
BIT 11
LSB
~
r--L
The analog input values given in Tables 2 and 3 are values that
BIn
SERIAL~""""
BIT 11
s-
should be present at the input to the internal ADC. The value
OUTPUT
MSB BIT 3
LSB
of the analog input will be affected by the gain of the
j ₎ d I ^. ANALO G IN ADC FULL SCALE
mo u e, I.e.,
"GAIN
PREVIOUS WORO, 111...11
NEW WORD,
101...01
Figure 5. ADC Timing Diagram
Set the ADC input voltage precisely to plus full scale minus
AMPLIFIER GAIN
1 1/2 LSB's: +4.9982V for 5V units, +9.9963V for :tlOV
units, +2.4982V for :t2.5V units, +4.9963V for :t5V units, or
+9.9926V for :tlOV units. Adjust the lOOn variable gain re-
sistor until binary and offset binary coded units are just on
The DAS1150 instrumentation amplifier gain may be set to any
any value between 1 and 1000 by connecting an external gain
resistor between pins 41 and 43. The resistance is determined
the verge of switching from 11111111111 0 to 111111111111
by the formula G = 1 + (2~k~ ). RG should be located as
and two's complement coded units are just on the verge of
close as possible to the module pins. It must be noted that the
switching from 011111111110 to 011111111111.
TC of RG directly affects the gain temperature coefficient of
INCREASING THROUGHPUT RATE
the DAS1150. A high quality metal film resistor 0.1 % is
recommended.
Throughput rates for the DAS1150 and DAS1151 can be
~
increased by the use of the OVERLAP MODE, i.e. updating
The gain of the DAS1151 is programmed by loading the
q
the input while the ADC is making a conversion. Typical
proper code into the gain address, as shown in Table 4.
::::>
z
throughput rates can be increased to 35kHz @ G = 1,
20kHz @ G = 1000 for the DAS1150 and 35kHz for G = 1
thm 8 for the DAS 1151. When the IA settling time is less
ADDRESS INPUTS DAS1151
Al Ao
GAIN
0
w_IZ-
than or equal to the sum of SHA acquisition time and ADC
00
1
eax..:
conversion time, 28Jls, the DAS throughput rate equals
01
2
1/28Jls or 35kHz. When IA settling time is greater than
10
4
28Jls (see Figure 4), the DAS throughput rate equals the
11
8
reciprocal of IA settling time.
Table 4. DAS1151 Gain State Truth Table
---