DAS1151_15 Datasheet, PDF (2/4 Pages) Analog Devices – LOW LEVEL INPUT 12 BIT DATA ACQUISITION MODULES

SPECIFICATIONS (typical @+25°Candratedsuppliesunlessothervyisenoted)
MODELS
RESOLUTION
CHARACTERISTICS
ADC Conversion Time
IA Settling
Time, 20V Input Step
to O.OI%@G = 1
to 0.01 % @ G = 10
to 0.05% @ G = 1000
Throughput Rate G = 1
G = 10
G = 1000
DAS1l50
12
25/1s max
15/1s max
15/1s
50/1s
25kHz
25kHz
13.3 kHz
(G = 1-8) 1OMsmax
N.A.
N.A.
= (G 1-8) 28.5kHz
N.A.
N.A.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
1---2.02151.3M1 A-IX ~
I
LU
-':::-;;:,2513.21 MIN
I 04~1~.71
UT
Sample-Hold
Acquisition Time
Aperture Delay Time
Aperture Time
Aperture Uncertainty Time
Droop Rate
3Ms
90ns
20ns
5ns
2mV/s
Overall Errorl @ G = 1
@ G = 1000
Nonlinearity Error
Offset Error
Gain Error
TEMPERATURE
OOffset (RTI)
Gain (RTI)
B ^Differential
COEFFICIENTS
) ^{S ANALOG INPUTS}
( ADC FS
Voltage Input Range \" GAIN
O ^{ADC Input Ranges}
LE _{Instrumentation Amplifier}
~ ^{T Gain}
Gain Range
\ ) ^{E Gain Equation}
Gain Ratio Error2
:tlLSB max
:t2LSB max
:tl/2LSB (:tlLSB
to Zero
to Zero
max)
/1V/DC
Reading/C
10mV to :tl0V
0 to +5V
0 to +10V
:t2.5V
:t5V
:tl0V
Resistor-Programmable
~ _.11~00(20H2
N.A. ^--
RG
(G = 8) :t2LSB max
4.02
1102.11
MAX
:t30/1V/C
*
0.625V to :tl0Y
So f tw are-Pro gramm a bIe
1,2,4,8
See Table 4
:to.02% FS max
BOTTOMVIEW --1 1--0., 12.541GRID
NOTES,
TERMINAL PINS INSTALLED ONLY IN SHADED
HOLE LOCATIONS.
SEE TABLE BELOW FOR PIN DELETIONS.
MODULE WEIGHT, 3.5 OUNCES 199.3 GRAMSI.
ALL PINS ARE GOLD PLATED HALF.HARD
BRASS IMIL.G..5204!. 0.019'" ".0°"" 10.40
'0.03mml DIA.
Input Impedance
1O8n
MATING SOCKET: AC1577
Bias Current
Offset Current
20nA
2nA
2nA
500pA
(4 per, $3 each)
Offset
(RTI)
:t50MV
DIGIT AL INPUTS
ADC Convert Command
SHA Mode Control
PGA Gain Control
Positive Pulse, TTL Compatible, lOOns
min Width
Positive Pulse TTL Compatible Logic
"1" = Hold, Logic "0" = Sample
N.A.
TTL Compatible,
DIGITAL OUTPUT
Parallel Data Output
Unipolar
Bipolar
Serial Data Output
Unipolar
Bipolar
Status Output
Clock
POWER REQUIREMENTS
TEMPERATURERANGE
Operating
Storage
PRICE
(1-24)
6TTL Loads/Bit
Positive True Binary
Positive True Offset Binary
or Two's Complement
6 TTL Loads
Positive True Binary NRZ Format,
MSB First
Positive True Offset Binaty, NRZ Format,
MSB First
Logic "1" During Conversion, TTL
Compatible, 4TTL Loads, Complement
also Available
480kHz, TTL Compatible, 6TTL Loads
+5V dc :t5% @ 130mA (170mA max)
:t15V dc :t3% @ 30mA (40mA max)
:t15V dc :t3% @ 30mA (40mA max)
0 to +70DC
-55DC to +85DC
$199
$249
NOTES
I Overall error is specified with gains and
offset trimmed and is defined as the
deviation from a straight line passing
through the end points of the range.
2Once the full scale has been calibrated
on any gain setting, switching to any
other gain setting will cause no more
than a 0.02% shift in full scale.
*Specifications same as DAS1150.
Specifications subject to change with-
out notice.
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