ADSP-218XN Datasheet, PDF (4/45 Pages) Analog Devices – DSP Microcomputer

ADSP-218xN Series
data/address pins and five control pins. The IDMA port
provides transparent, direct access to the DSP’s on-chip
program and data RAM.
An interface to low-cost byte-wide memory is provided by
the Byte DMA port (BDMA port). The BDMA port is
bidirectional and can directly address up to four megabytes
of external RAM or ROM for off-chip storage of program
overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
(BR, BGH, and BG). One execution mode (Go Mode)
allows the ADSP-218xN to continue running from on-chip
memory. Normal execution mode requires the processor to
halt while buses are granted.
ADSP-218xN series members can respond to eleven inter-
rupts. There can be up to six external interrupts (one edge-
sensitive, two level-sensitive, and three configurable) and
seven internal interrupts generated by the timer, the serial
ports (SPORT), the Byte DMA port, and the power-down
circuitry. There is also a master RESET signal. The two
serial ports provide a complete synchronous serial interface
with optional companding in hardware and a wide variety
of framed or frameless data transmit and receive modes of
operation.
Each port can generate an internal programmable serial
clock or accept an external serial clock.
ADSP-218xN series members provide up to 13 general-
purpose flag pins. The data input and output pins on
SPORT1 can be alternatively configured as an input flag
and an output flag. In addition, eight flags are programma-
ble as inputs or outputs, and three flags are always outputs.
A programmable interval timer generates periodic inter-
rupts. A 16-bit count register (TCOUNT) decrements
every n processor cycle, where n is a scaling value stored
in an 8-bit register (TSCALE). When the value of the count
register reaches zero, an interrupt is generated and the
count register is reloaded from a 16-bit period register
(TPERIOD).
Serial Ports
ADSP-218xN series members incorporate two complete
synchronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-
218xN SPORTs. For additional information on Serial
Ports, refer to the ADSP-218x DSP Hardware Reference.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or
with frame synchronization signals internally or externally
generated. Frame sync signals are active high or inverted,
with either of two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to
16 bits and provide optional A-law and µ-law compand-
ing, according to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate
unique interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively
receive and transmit a 24 or 32 word, time-division mul-
tiplexed, serial bitstream.
• SPORT1 can be configured to have two external inter-
rupts (IRQ0 and IRQ1) and the FI and FO signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONS
ADSP-218xN series members are available in a 100-lead
LQFP package and a 144-Ball Mini-BGA package. In order
to maintain maximum functionality and reduce package size
and pin count, some serial port, programmable flag, inter-
rupt and external bus pins have dual, multiplexed function-
ality. The external bus pins are configured during RESET
only, while serial port pins are software configurable during
program execution. Flag and interrupt functionality is
retained concurrently on multiplexed pins. In cases where
pin functionality is reconfigurable, the default state is shown
in plain text in Table 2, while alternate functionality is
shown in italics.
–4–
REV. 0