ADSP-218XN Datasheet, PDF (15/45 Pages) Analog Devices – DSP Microcomputer

ADSP-218xN Series
Memory-Mapped Registers (New to the ADSP-218xM
and N series)
ADSP-218xN series members have three memory-mapped
registers that differ from other ADSP-21xx Family DSPs.
The slight modifications to these registers (Wait State Con-
trol, Programmable Flag and Composite Select Control,
and System Control) provide the ADSP-218xN’s wait state
and BMS control features. Default bit values at reset are
shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a grey field. These bits should
always be written with zeros.
I/O Space (Full Memory Mode)
ADSP-218xN series members support an additional exter-
nal memory space called I/O space. This space is designed
to support simple connections to peripherals (such as data
converters and external registers) or to bus interface ASIC
data registers. I/O space supports 2048 locations of 16-bit
wide data. The lower eleven bits of the external address bus
are used; the upper three bits are undefined.
Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait
state registers, IOWAIT0–3 as shown in Figure 9, which in
combination with the wait state mode bit, specify up to 15
wait states to be automatically generated for each of four
regions. The wait states act on address ranges, as shown
in Table 10.
Note: In Full Memory Mode, all 2048 locations of I/O space
are directly addressable. In Host Memory Mode, only
address pin A0 is available; therefore, additional logic is
required externally to achieve complete addressability of the
2048 I/O space locations.
Table 10. Wait States
Address Range
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
Wait State Register
IOWAIT0 and Wait State Mode
Select Bit
IOWAIT1 and Wait State Mode
Select Bit
IOWAIT2 and Wait State Mode
Select Bit
IOWAIT3 and Wait State Mode
Select Bit
WAIT STATE CONTROL
W01 _{==AIRN2TN1AO15SNR+TGM1A11I4DATNMWELGO1A1MM3FDITROOE1ODD12(PMEEW1I(S01OP1AI}ETWW_nILOT1sEAA1,0_eC7IID_{rTT)TtW,391WDAWIaT8I1Ai}^O,t_IIWTO^S_,71AW^t_I^a_OIAT^t_W^e26I1TAC_0I–IT^{o51O30nW–=t}_3A^r412o_=INT^l_N1+3^R1 _W1^eg_AW21I^iOIs_AT^tWIe_ST11A^r_{TSIATT0T10AETSE,DSM,} ^(0X3FFE)
RANGING FROM 0 TO 15)
Figure 9. Wait State Control Register
Composite Memory Select
ADSP-218xN series members have a programmable
memory select signal that is useful for generating memory
select signals for memories mapped to more than one space.
The CMS signal is generated to have the same timing as
each of the individual memory select signals (PMS, DMS,
BMS, IOMS) but can combine their functionality. Each bit
in the CMSSEL register, when set, causes the CMS signal
to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in
the CMSSEL register and use the CMS pin to drive the chip
select of the memory, and use either DMS or PMS as the
additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable
bit causes the assertion of the CMS signal at the same time
as the selected memory select signal. All enable bits default
to 1 at reset, except the BMS bit.
See Figure 10 and Figure 11 for illustration of the program-
mable flag and composite control register and the system
control register.
PROGRAMMABLE FLAG AND COMPOSITE
SELECT CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11 11101100000000
DM(0X3FE6)
BMWAIT
CMSSEL
PFT YP E
0 = D ISA BL E CMS 0 = IN PU T
1 = ENA BL E CMS 1 = O UT PUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
Figure 10. Programmable Flag and Composite Control
Register
REV. 0
–15–