AD9650-EP Datasheet, PDF (4/12 Pages) Analog Devices – Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter

AD9650-EP
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 2.
Parameter¹
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 30 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
CROSSTALK²
ANALOG INPUT BANDWIDTH
Temperature Min
25°C
Full
78.4
25°C
Full
77.9
25°C
25°C
Full
25°C
Full
87
25°C
Full
Full
25°C
Typ
Max
80.5
80.2
13
−93
−87
93
−101
−94
−105
500
Unit
dBFS
dBFS
dBFS
dBFS
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
MHz
1 _{See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.}
2 _{Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.}
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature Min
Full
Full
0.3
Full
AGND
Full
0.9
Full
−100
Full
−100
Full
Full
8
Full
Full
AGND
Full
1.2
Full
AGND
Full
−100
Full
−100
Full
Full
12
Typ
Max
CMOS/LVDS/LVPECL
0.9
3.6
AVDD
1.4
+100
+100
9
10
12
CMOS
0.9
1
16
AVDD
AVDD
0.6
+100
+100
20
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
V
V
µA
µA
pF
kΩ
Rev. 0 | Page 4 of 12