AD9650-EP Datasheet, PDF (1/12 Pages) Analog Devices – Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter

Data Sheet
FEATURES
Dual 16-bit ADC in enhanced package for extended
temperature range of −55°C to +85°C
1.8 V analog supply operation
LVDS output
SNR: 80.5 dBFS at 30 MHz input and 105 MSPS data rate
SFDR: 93 dBc at 30 MHz input and 105 MSPS data rate
Low power: 328 mW per channel at 105 MSPS
Integer 1-to-8 input clock divider
IF sampling frequencies up to 300 MHz
Analog input range of 2.7 V p-p
Optional on-chip dither
Integrated ADC sample-and-hold inputs
Differential analog inputs with 500 MHz bandwidth
ADC clock duty cycle stabilizer (DCS)
APPLICATIONS
Radar
Electronic warfare (EW) systems
Joint tactical radio system (JTRS) and other COMSEC
Industrial instrumentation
X-ray, MRI, and ultrasound equipment
High speed pulse acquisition
Chemical and spectrum analysis
General-purpose software radios
GENERAL DESCRIPTION
The AD9650-EP is a dual 16-bit, 105 MSPS analog-to-digital
converter (ADC) designed for digitizing high frequency, wide
dynamic range signals with input frequencies of up to 300 MHz.
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold analog
input amplifiers, and a shared integrated voltage reference, which
eases design considerations. A duty cycle stabilizer (DCS) is pro-
vided to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC output data can be routed directly to the two external
16-bit output ports or multiplexed on a single 16-bit bus. These
outputs can be set to either 1.8 V CMOS or LVDS.
Flexible power-down options allow significant power savings,
when desired. Programming for setup and control is accomplished
using a 3-wire, SPI-compatible serial interface.
The AD9650-EP is available in an 80-lead TQFP and is specified
over the extended temperature range of −55°C to +85°C.
Rev. 0
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Dual 16-Bit, 105 MSPS, 1.8 V
Analog-to-Digital Converter
AD9650-EP
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO/ SCLK/
DCS DFS ^CSB
DRVDD
AD9650-EP
SPI
VIN+A
VIN–A
ADC
PROGRAMMING DATA
CMOS/LVDS ¹⁶
OUTPUT BUFFER
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
ADC
MULTICHIP
SYNC
DIVIDE 1
TO 8
DUTY CYCLE
DCO
STABILIZER GENERATION
CMOS/LVDS ¹⁶
OUTPUT BUFFER
AGND SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE LVDS PIN CONFIGURATION ONLY.
Figure 1.
OR+
D15+ (MSB)
TO
D0+ (LSB)
CLK+
CLK–
DCO+
DCO–
OR–
D15– (MSB)
TO
D0– (LSB)
Additional application and technical information can be found
in the AD9650 data sheet.
PRODUCT HIGHLIGHTS
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply with a separate digital
output driver supply that accommodates 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions such as data formatting
(offset binary, twos complement, or Gray coding), enabling
the clock DCS, power-down, and test modes.
5. 12 mm × 12 mm, 80-lead TQFP with an exposed pad
(7.5 mm × 7.5 mm).
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